Fairchild Semiconductor TMC2250AX2 Datasheet

www.fairchildsemi.com
REV. 1.0.2 10/25/00
Features
• Four user-selectable filtering and transformation functions: – Triple dot product (3 x 3) matrix multiply – Cascadeable 9-tap systolic FIR filter – Cascadeable 3 x 3-pixel image convolver – Cascadeable 4 x 2-pixel image convolver
• 50 MHz (20ns) pipelined throughput
• 12-bit input and output data, 10-bit coefficients
• 6-bit cascade input and output ports in all filter modes
• Onboard coefficient storage, with three-cycle updating of all nine coefficients
Applications
• Image filtering and manipulation
• Video effects generation
• Video standards conversion and encoding/decoding
• Three-dimensional image manipulation
• Medical image processing
• Edge detection for object recognition
• FIR filtering for communications systems
Description
The TMC2250A is a flexible high-performance nine-multiplier array VLSI circuit which can execute a cascadeable 9-tap FIR filter, a cascadeable 4 x 2 or 3 x 3-pixel image convolu­tion, or a 3 x 3 color space conversion. All configurations offer throughput at up to the maximum guaranteed 50 MHz clock rate with 12-bit data and 10-bit coefficients. All inputs and outputs are registered on the rising edges of the clock.
The 3 x 3 matrix multiply or color conversion configuration can perform video standard conversion (YIQ or YUV to RGB, etc.) or three-dimensional perspective translation at real-time video rates.
The 9-tap FIR filter configuration, useful in Video, Telecom­munications, and Signal Processing, features a 16-bit cascade input to allow construction of longer filters.
The cascadeable 3 x 3 and 4 x 2-pixel image convolver func­tions allow the user to perform numerous image processing functions, including static filters and edge detectors. The 16-bit cascade input port facilitates two-chip 50 MHz cubic convo­lution (4 x 4-pixel kernel).
The TMC2250A is fabricated in a sub-micron CMOS process and operates at clock speeds of up to 50 MHz over the full commercial (0°C to 70°C) temperature and supply voltage ranges. It is available in 120-pin Plastic Pin Grid Array (PPGA) packages, 120-lead Ceramic Pin Grid Array pack­age (CPGA), 120-lead PQFP to PPGA package (MPGA) and 120-lead Plastic Quad FlatPack (PQFP). All input and output signals are TTL compatible.
TMC2250A
Matrix Multiplier
12 x 10 bit, 50 MHz
PRODUCT SPECIFICATION TMC2250A
2
REV. 1.0.2 10/25/00
Functional Description
The TMC2250A is a nine-multiplier array with the internal bus structure and summing adders needed to implement a 3 x 3 matrix multiplier (triple dot product) a cascadeable 9-tap FIR filter, a 3 x 3-pixel convolver, or a 4 x 2-pixel convolver all in one monolithic circuit. With a 50MHz guaranteed maximum clock rate, this device offers video and imaging system designers a single-chip solution to numerous common image and signal-processing problems.
The three data input ports (A, B, C) accept 12-bit two's com­plement integer data, which is also the format for the output ports (X, Y, Z) in the matrix multiply mode (Mode 00). In the filter configurations (Modes 01, 10, and 11) the cascade ports assume 12-bit integer, 4-bit fractional two's complement data on both input and output. The coefficient input ports (KA, KB, KC) are always 10-bit two's complement fractional. Table 1 details the bit weighting of the input and output data in all configurations.
Operating Modes
The TMC2250A can implement four different digital filter architectures. Upon selection of the desired function by the user (MODE
1-0
), the device reconfigures its internal data paths and input and output buses appropriately. The output ports (XC, YC and ZC) are configured in all filter modes a 16-bit Cascade In and Cascade Out ports so that multiple devices can be connected to build larger filters. These modes are described individually below. The I/O function configu­rations for all four modes are shown in Table 1.
Definitions
The calculations performed by the TMC2250A in each mode are also shown below, utilizing the following notation:
A(1), B(5), C(2), CASIN(3)
Indicates the data word presented to that input port during the specified clock rising edge(x). Applies to all input ports A
11-0
, B
11-0
, C
11-0
, and CASIN
15-0
.
KA1(1), KB3(4)
Indicates coefficient data stored in the specified one of the nine onboard coefficient registers KA1 through KC3, as shown in the block diagram for that mode, input during or before the specified clock rising edge (x).
X(1), Y(4), Z(6), CASOUT (6)
Indicated data available at that output port t
DO
after that specified clock rising edge (x). Applies to all output ports X
11-0
, Y
11-0
, Z
11-0
, and CASOUT
15-0
.
Numeric Format
Table 2 shows the binary weightings of the input and output ports of the TMC2250A. Although the internal sums of prod­ucts could grow to 23 bits, in the matrix multiply mode (Mode 00) the outputs X, Y and Z are rounded to yield 12-bit integer words. Thus the output format is identical to the input data format. In the filter configurations (Modes 01, 10, and
11) the cascade output is always half-LSB rounded to 16 bits, specifically 12 integer bits and 4 fractional guard bits, with no overflow "headroom". The user is of course free to half-LSB round the output word to any size less than 16 bits by forcing a 1 into the bit position of the cascade input immediately below the desired LSB. In all modes, bit weighting is easily adjusted if desired by applying the same scaling correction factor to both input and output data words. If the coefficients are rescaled, the relative weightings of the CASIN and CASOUT ports will differ accordingly.
Data Overflow
As shown in Table 2, the TMC2250A's matched input and output data formats accommodate 0dB (unity) gain. There­fore, the user must be aware of input conditions that could lead to numeric overflow. Maximum input data and coeffi­cient word sizes must be taken into account with the specific algorithm performed to ensure that no overflow occurs.
Table 1. Data Port Formatting by Mode
Mode
Inputs Inputs/Output Outputs
A
11-0
B
11-0
C
11-0
KA
9-0
KB
9-0
KC9-0 XC
11-0
YC
11-8
Y
7-4
YC3-0 ZC
11-0
00 A
11-0
B
11-0
C
11-0
KA
9-0
KB
9-0
KC9-0 X
11-0
Y
11-8
Y
7-4
Y
3-0
Z
11-0
01 A
11-0
B
11-0
NC KA
9-0
KB
9-0
KC9-0 CASIN
15-4
CASIN
3-0
NC CASOUT
3-0
CASOUT
15-4
10 A
11-0
B
11-0
C
11-0
KA
9-0
KB
9-0
KC9-0 CASIN
15-4
CASIN
3-0
NC CASOUT
3-0
CASOUT
15-4
11 A
11-0
B
11-0
NC KA
9-0
KB
9-0
KC9-0 CASIN
15-4
CASIN
3-0
NC CASOUT
3-0
CASOUT
15-4
TMC2250A PRODUCT SPECIFICATION
REV. 1.0.2 10/25/00
3
Table 2. Bit Weightings for Input and Output Data Words
Note: A minus sign indicates a two’s complement sign bit.
Bit Weights 2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
.2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
Inputs
All Modes Data A, B, C
-I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
.
Coefficients KA, KB, KC
-K
9
.K
8
K
7
K
6
K
5
K
4
K
3
K
2
K
1
K
0
Modes 01, 10, 11 CASIN
-CI
15
CI
14
CI
13CI12CI11CI10CI9CI8CI7CI6CI5CI4
.CI3CI2CI1CI
0
Internal Sum X20X19X18X17X16X15X14X13X12X11X10X9.X8X7X6X5X4X3X2X1X
0
Outputs
Mode 00 X, Y, Z
-O
11O10O9O8O7O6O5O4O3O2O1O0
.
Modes 01, 10, 11 CASOUT
-
CO
15
CO
1
4
CO
1
3
CO
1
2
CO
1
1
CO
1
0CO9CO8CO7CO6CO5
CO4.CO3CO2CO1CO
0
PRODUCT SPECIFICATION TMC2250A
4 REV. 1.0.2 10/25/00
Pin Assignments
120 Pin Plastic Quad Flat Pack (MQFP), KE Package
XC
6
XC
5
XC
4
XC
3
XC
2
XC
1
XC
0
GND YC
11
YC
10
YC
9
V
DD
YC
8
Y
7
Y
6
GND Y
5
Y
4
YC
0
V
DD
YC
1
YC
2
YC
3
GND ZC
0
ZC
1
ZC
2
ZC
3
ZC
4
ZC
5
1
30
120 91
31 60
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90
61
ZC
6
ZC
7
ZC
8
GND ZC
9
ZC
10
ZC
11
KC
0
KC
1
KC
2
KC
3
GND KC
4
KC
5
KC
6
V
DD
KC
7
KC
8
KC
9
KB
0
KB
1
KB
2
KB
3
KB
4
KB
5
KB
6
KB
7
KB
8
KB
9
KA
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pin Name Pin Name
KA
1
KA
2
KA
3
KA
4
KA
5
KA
6
KA
7
KA
8
KA
9
CWE
1
CWE
0
GND A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
B
0
B
1
B
2
CLK B
3
B
4
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
B
5
B
6
B
7
B
8
B
9
B
10
B
11
C
0
C
1
C
2
C
3
V
DD
C
4
C
5
C
6
GND C
7
C
8
C
9
C
10
C
11
MODE
1
MODE
0
GND XC
11
XC
10
XC
9
V
DD
XC
8
XC
7
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin Name Pin Name
TMC2250A PRODUCT SPECIFICATION
REV. 1.0.2 10/25/00 5
Pin Assignments (continued)
120 Pin Plastic Pin Grid Array, H5 Package and 120 Pin Ceramic Pin Grid Array, G1 Package and 120 Pin Plastic Quad Flatpack to 120-Pin Pin Grid Array (MPGA)
BADEFGHJKLMNC
1
2
3
4
5
6
7
8
9
10
11
12
13
Top View Cavity Up
KEY
XC
7
XC
9
XC
10
MODE
0
C
11
C
8
C
7
C
5
C
3
C
1
B
10
B
7
B
4
XC
4
XC
5
XC
8
XC
11
MODE
1
C
9
C
6
C
4
C
2
B
11
B
9
B
6
B
2
XC
1
XC
2
XC
6
V
DD
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4
GND C
10
GND V
DD
C
0
B
8
B
5
B
3
B
1
YC
11
XC
0
XC
0
CLK B
0
A
10
YC
9
YC
10
GND A
11
A
9
A
8
Y
7
YC
8
V
DD
A
7
A
6
A
5
Y
5
Y
6
GND
C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3
Pin Name Pin Name
A
3
A
2
A
3
Y
4
YC
0
V
DD
GND A
0
A
1
YC
1
YC
2
GND KA
8
CWE
1
CWE
0
YC
3
ZC
0
ZC
3
KA
4
KA
7
KA
9
ZC
1
ZC
4
ZC
6
GND KC
0
GND V
DD
KB
0
KB
4
G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9
KB
8
KA
1
KA
5
KA
6
ZC
2
ZC
7
ZC
9
ZC
11
KC
2
KC
4
KC
6
KC
9
KB
2
KB
5
KB
9
KA
2
KA
3
ZC
5
ZC
8
ZC
10
KC
1
KC
3
KC
5
KC
7
KC
8
KB
1
KB
3
KB
6
KB
7
KA
0
L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13
Pin Name Pin Name
PRODUCT SPECIFICATION TMC2250A
6 REV. 1.0.2 10/25/00
Pin Descriptions
Pin Name
Pin Number
Function Pin Description
CPGA/PPGA/
MPGA
MQFP
Power
V
DD
F3, H3, L7, C8, C412, 20, 46,
102, 118
Supply Voltage
The TMC2250A operates from a single +5V supply. All pins must be connected.
GND E3, G3, J3, L4,
L6, H11, C7,
C5
8, 16, 24, 34,
42, 72, 106,
114
Ground The TMC2250A operates from a single +5V supply.
All pins must be connected.
Clock
CLK D11 88 System Clock The TMC2250A operates from a single system clock
input. All timing specifications are referenced to the rising edge of clock.
Controls
MODE
1,0
B4, A4 112, 113 Mode Control The TMC2250A will switch to the configuration
selected by the user (as shown in Table 3) on the next clock. This registered control is usually static; however, should the user wish to switch between modes, the internal pipeline latencies of the device must be taken into account. Valid data will not be available at the outputs in the new configuration until enough clocks in the new mode have passed to flush the internal registers.
CWE
1,0
J12, J13 70, 71 Coefficient
Write Enable
Data presented to the coefficient input ports (KA, KB, and KC) will update three of the internal coefficient storage registers, as indicated by the simultaneous Coefficient Write Enable select, on the next clock. See Table 4 and the Functional Block Diagram.
Input/Output
A
11-0
E11, D13, E12,
E13, F11, F12,
F13, G13,
G11, G12,
H13, H12
84, 83, 82, 81, 80, 79, 78, 77,
76, 75, 74, 73
Data Input A Data presented to the 12-bit registered data input
ports A, B, and C are latched into the multiplier input registers for the currently selected configuration (Table 3). In all modes except Mode 00, new data are internally right-shifted to the next filter tap on each rising edge of CLK.
B
11-0
B10, A11, B11, C10, A12, B12,
C11, A13, C12, B13,
C13, D12
97, 96, 95, 94, 93, 92, 91, 90,
89, 87, 86, 85
Data Input B
C
11-0
A5, C6, B6, A6, A7, B7, A8, B8,
A9, B9, A10,
C9
111, 110, 109, 108, 107, 105, 104, 103,
101, 100, 99,
98
Data Input C
TMC2250A PRODUCT SPECIFICATION
REV. 1.0.2 10/25/00 7
Notes:
1. The output ports X, Y, Z and CASOUT, and input port CASIN are internally reconfigured by the device as required for each mode of the device. The multiple-function pins have names which are combinations of these titles, as appropriate.
2. The output drivers on pins XC
11-0
and YC
11-8
are not necessarily disabled until after the first rising edge of CLK following
power-up. If these pins are to be tied to other output drivers, to each other, or to ground or V
DD
, the user should ensure that
a clock pulse arrives within a few seconds of power-up, to avoid bus contention.
KA
9-0
K13, J11, K12, L13, L12, K11,
M13, M12,
L11, N13
69, 68, 67, 66, 65, 64, 63, 62,
61, 60
Coefficient Input A1, A2, A3
Data presented to the 10-bit registered coefficient input ports KA, KB and KC are latched three at a time into the internal coefficient storage register set indicated by the Coefficient Write Enable CWE
1,0
on
the next clock, as shown in Table 4.
KB
9-0
M11, L10,
N12, N11,
M10, L9, N10,
M9, N9, L8
59, 58, 57, 56, 55, 54, 53, 52,
51, 50
Coefficient Input B1, B2, B3
KC
9-0
M8, N8, N7, M7, N6, M6,
N5, M5, N4, L5
49, 48, 47, 45, 44, 43, 41, 40,
39, 38
Coefficient Input B1, B2, B3
XC
11-0
B4, A3, A2, B3, A1, C3, B2, B1, D3, C2, C1, D2
115, 116, 117, 119,
120, 1, 2, 3, 4,
5, 6, 7
CASIN
15-4
/
Output X
In all modes except Mode 00, the x port and four bits of the Y output port are reconfigured as the 16-bit registered Cascade Input port CASIN
15-0
. Data presented to this input will be added to the weighted sums of the data words which were presented to the input ports (A, B and C). In the matrix multiply mode, data are available at the 12-bit registered output ports X, Y AND Z tDO after every clock. These ports are reconfigured in the filtering modes as 16-bit Cascade Input and Output ports.CASOUT
15-0
In all modes except Mode 00, the Z port and four bits of the Y output port are reconfigured as the 16-bit registered Cascade Output port CASOUT
15-0
.
YC
11-8
D1, E2, E1, F2 9, 10, 11, 13 CASIN
3-0
/
Output Y
11-0
Y
7-4
F1, G2, G1, H1 14, 15, 17, 18 Output
7-4
only
YC
3-0
K1, J2, J1, H2 23, 22, 21, 19 CASOUT
3-0
/
Output Y
3-0
ZC
11-0
M4, N3, M3,
N2, M2, L3, N1, L2, K3,
M1, L1, K2
37, 36, 35, 33, 32, 31, 30, 29,
28, 27, 26, 25
CASOUT
15-4
/
Output Z
11-0
Pin Descriptions (continued)
Pin Name
Pin Number
Function Pin Description
CPGA/PPGA/
MPGA
MQFP
Table 3. Conguration Mode Word Table 4. Coefcient Write Enable Word
MODE
1,0
Conguration Mode
00 3 x 3 Matrix Multiply
01 9-Tap One Dimensional FIR
10 3 x 3 -Pixel Convolver
11 4 x 2 -Pixel Convolver
CWE
1,0
Coefcient Set Selected
00 Hold all registers
01 Update KA1, KB1, KC1
10 Update KA2, KB2, KC2
11 Update KA3, KB3, KC3
Loading...
+ 16 hidden pages