Fairchild Semiconductor TMC2242B, TMC2242A Datasheet

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TMC2242A/TMC2242B

Digital Half-Band Interpolating/Decimating Filter

12-bit In/16-bit Out, 60 MHz

Features

• TMC2242A and TMC2242B are pin-compatible with
TMC2242

• User selectable interpolate gain, -6 dB or 0 dB (2242B)

• 30, 40 and 60 MHz speed grades

• User selectable 2:1 decimation, 1:2 interpolation, and
equal-rate filter modes

• Passband ripple <

• Stopband rejection 59.4 dB from 0.28 to 0.50 x f

• Cascading two TMC2242A or TMC2242B meets
CCIR 601 low-pass filter requirement

• Dedicated 12-bit 2's complement input data port and
16-bit output data port with user-selectable rounding from
9 to 16 bits

• Two's complement or offset binary output format

• Built-in limiter prevents overflow

±

0.01 dB

s

• Single +5 Volt power supply operation

• Small 44-Lead PLCC and 44-Lead MQFP

Applications

• Low-cost video filtering

• Chrominance bandwidth limiter

• Simple, inexpensive video D/A post-filters

• Reduced cost and complexity for A/D anti-aliasing filters

• High-performance digital low-pass filters

• Digital waveform reconstruction post-filtering

• Telecommunications

• Direct digital synthesis

• Radar

Description

The TMC2242A and TMC2242B are fixed-coefficient lin­ear-phase half-band (low-pass) digital filters. They can be
used to halve or double the sampling rate of a digital signal.
When used as a decimating post-filter with a double-speed
oversampling A/D con verter , they greatly reduce the cost and
complexity of anti-aliasing filters required ahead of the A/D
converter. When used as an interpolating pre-filter with a
double-speed oversampling D/A converter, the TMC2242A
and TMC2242B significantly reduce the design complexity
and production cost of reconstruction filters used on D/A
outputs.

Block Diagram

12

Control

55 Tap

12

Decimate, Equal Rate 1-1-1-1

12 16

Interpolate 0-1-0-1

SI

11-0

CLK

DEC

INT

SYNC

12

The TMC2242A and TMC2242B user selects the mode of
operation (decimate, interpolate, or equal-rate) and round­ing. The TMC2242A and TMC2242B accept 12-bit 2's com­plement data at up to 60 MHz and output saturated
(overflow-protected) 2's complement or offset binary data
rounded to from 9 to 16 bits. Within the speed grade I/O
limit, the output sample rate may be 1/2, 1, or 2 times the
input sample rate.

OE

FIR

Filter

Round

and

Limit

3

16

16

65-2242A-01

SO

TCO
RND

2-0

15-0

Rev. 1.2.0

2

PRODUCT SPECIFICATION TMC2242A/TMC2242B

Description

The filter response is flat to within

0.22 x f

from 0.28 x f
down at 0.25 x f

, with stopband attenuation greater than 59.4 dB

s

(continued)

±

0.01 dB from 0.00 to

to the Nyquist frequency . The response is 6 dB

s

. Symmetric-coefficient filters such as the

s

TMC2242A and TMC2242B have linear phase response.
Full compliance with the CCIR-601 standard of 12 dB atten­uation at 0.25 x f

is achieved by cascading two parts.

s

The TMC2242A and TMC2242B are fabricated on an
advanced submicron CMOS process. They are available in a
44-lead J-lead PLCC package. Performance is guaranteed
from 0

°

C to 70

°

C.

Functional Description

The TMC2242A and TMC2242B implement a fixed-coeffi­cient linear-phase Finite Impulse Response (FIR) filter of 55
effective taps, with special rate-matching input and output
structures to facilitate 2:1 decimation and 1:2 interpolation.
The faster of either the input or output registers will operate
at the guaranteed maximum clock rate (speed grade). The
total internal pipeline latency from the input of an impulse to
the corresponding output peak (digital group delay) is 34
cycles; the 55-value output response begins after 7 clock
cycles and ends after 61 cycles.

To perform interpolation, the chip slows the effective input
register clock rate to half the output rate. It internally inserts
zeroes between the incoming data samples to "pad" the input
data rate to match the output rate.

To perform decimation, the chip sets the output register
clock rate to half of the input rate. One output is then
obtained for every two inputs.

For interpolation, the user should bring SYNC HIGH for at
least one clock cycle, returning it LOW with the first desired
input data value. When interpolating, the chip will then con­tinue to accept a new data input on each alternate rising edge
of the clock. When decimating, the chip will present one out­put value for every two clock cycles. The user may leave
SYNC LOW or toggle it once per rising clock edge, with
equivalent performance.

The output data format is two's complement if TCO is
HIGH, inverted of fset binary if LOW. The user can tailor the
output data word width to his/her system requirements using
the Rounding control. As shown in Table 4, the output is
half-LSB rounded to the resolution selected by the value of
RND

. The asynchronous three-state output enable control

2-0

simplifies connection to a data bus with other drivers.

Table 1. Operating Modes

DEC

Note:

1. With 15-bit overflow protection. All other modes on both

INT TMC2242A TMC2242B

0 0 Equal Rate Interpolate (0 dB)
0 1 Decimate Decimate
1 0 Interpolate (-6 dB) Interpolate (-6 dB)
1 1 Equal Rate Equal Rate

parts limit to 16 bits.

1

Pin Assignments

SO
SO
SO

SO
SO

GND

V
SO
SO
SO
SO

DD

SO13SO14SO15OE

65432

7

12

8

11

9

10

10

9

11

8

12
13
14

7

15

6

16

5

17

4

1819202122232425262728

SO3SO2SO1SO

TCO

DEC

INT

1

4443424140

TMC2242A
TMC2242B

0

0

RND2RND1RND

44 Lead PLCC

SYNC

SI0SI1SI

CLK

GND

2

11

SI

39
38
37
36
35
34
33
32
31
30
29

GND

GND
V

DD

SI

10

SI

9

SI

8

SI

7

SI

6

SI

5

SI

4

SI

3

V

DD

65-2242A-02

SO
SO
SO

SO
SO

GND

V
SO
SO
SO
SO

DD

SO13SO14SO15OE

4443424140393837363534

1

12

2

11

3

10

4

9

5

8

6
7
8

7

9

6

10

5

11

4

1213141516171819202122

SO3SO2SO1SO

TCO

DEC

TMC2242A
TMC2242B

0

RND2RND1RND

INT

0

SYNC

SI0SI1SI

CLK

GND

2

11

SI

33
32
31
30
29
28
27
26
25
24
23

GND

GND
V

DD

SI

10

SI

9

SI

8

SI

7

SI

6

SI

5

SI

4

SI

3

V

DD

65-2242A-02

44 Lead MQFP

TMC2242A/TMC2242B PRODUCT SPECIFICATION

Pin Descriptions

Pin Number
Pin Name
Timing Controls

INT

44 38

Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at

1/2 the CLK rate and zeros are inserted in the data stream between valid input
values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and
output results at the full CLK rate.

DEC 139 Decimate. When DEC is LOW and INT is HIGH, the input data register runs at

the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and
output results at 1/2 the CLK rate.

When INT

= DEC, the TMC2242A is in equal rate mode. When both INT and DEC
are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and
DEC are LOW, the TMC2242B interpolates with unity gain.

In equal-rate mode, the input and output sample rates equal the chip clock rate.

SYNC 43 37

Synchronization. Incoming data are synchronized by holding SYNC HIGH on

CLK N–1 and LOW on CLK N when the first input data word is present on SI
If DEC

= INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW

until resynchronization is desired, or it may be toggled at 1/2 the CLK rate.

CLK 42 36

Clock. The TMC2242A and TMC2242B operate from a single master clock. All

internal registers, except the output register in decimation mode, are strobed on
the rising edge of CLK. All timing parameters are referenced to the rising edge of
CLK.

Data Inputs

SI

11-0

40,
37-30,
27-25

34,
31-24,
21-19

Input Data Port. A 12-bit 2's-complement input word is registered by the rising

edge of CLK. In Interpolate Mode, SI
(synchronized by SYNC). SI

Data Outputs

SO

15-0

4-11,
14-21

42-44,
1-5,
8-15

Output Data Port. A 16-bit 2's-complement output result is available after the

rising edge of CLK. In Decimate Mode, SO
(synchronized by SYNC). SO
SO

is the MSB.

15

The limiter circuitry ensures that for internal overflow, a valid full-scale output
(7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with

-6dB gain, limits are 3FFF and C000 (TCO=1).

Output Controls

OE

341 Output Enable. When LOW, SO

high-impedance state. OE

TCO 2 40

Output Format. When TCO is HIGH, output data are in signed 2's-complement

format. When LOW, the output is inverted offset binary.

RND

2-0

22-24 16-18 Rounding Select. These inputs set the position of the effective LSB of the output

result. Outputs below the rounding bit are zeroed (Table 4).

Power

V

DD

GND 12,28,

13,29,387, 23,

32
6, 22,

39,41

33, 35

Supply Voltage. +5 Volt power inputs. These should come from the same power

source and be decoupled to GND.

Ground. Ground inputs should be connected to the system digital ground plane.

Pin Function DescriptionPLCC MQFP

is registered on every other CLK

11-0

is the MSB.

11

is registered on every other CLK

is rounded according to the state of RND

15-0

15-0

15-0

are enabled. When HIGH, SO

is asynchronous with respect to CLK.

15-0

11-0

.

2-0

are in a

.

3

C

PRODUCT SPECIFICATION TMC2242A/TMC2242B

Absolute Maximum Ratings

(beyond which the device may be damaged)

Parameter Conditions Min Max Units

Supply Voltage -0.5 7.0 V
Input Voltage -0.5 V
Output Applied Voltage
Externally Forced Current

2

3,4

Short Circuit Duration Single output in HIGH state to ground 1 sec
Operating Temperature (Case) -20 110
Junction Temperature 140
Lead Soldering Temperature 10 seconds 300
Storage Temperature -65 150

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specified range.

3. Forcing voltage must be limited to specified range.

4. Current is specified as conventional current flowing into the device.

1

+ 0.5 V

DD

-0.5 V

+ 0.5 V

DD

-3.0 +6.0 mA

°

C

°

C

°

C

°

Operating Conditions

Parameter Conditions Min Nom Max Units

V
f

CLK

Power Supply Voltage 4.75 5.0 5.25 V

DD

Clock frequency TMC2242A, B 30 MHz

TMC2242A-1,B-1 40 MHz
TMC2242A-2,B-2 60 MHz

t

PWH

t

PWL

t

S

t

H

V
V
I

OH

I

OL

T

CLK pulse width, HIGH 6 ns
CLK pulse width, LOW 6 ns
Input Data Set-up Time 6 ns
Input Data Hold Time 1 ns
Input Voltage, Logic HIGH 2.0 V

IH

Input Voltage, Logic LOW 0.8 V

IL

Output Current, Logic HIGH -2.0 mA
Output Current, Logic LOW 4.0 mA
Ambient Temperature, Still Air 0 70

A

°

C

4

TMC2242A/TMC2242B PRODUCT SPECIFICATION

Electrical Characteristics

Parameter Conditions Min Typ Max Units

I

DD

I

DDU

I

DDQ

C
I

IH

I

IL

I

OZH

I

OZL

I

OS

V
V

Total Power Supply
Current

V

= Max, C

DD

LOAD

=25pF, f

CLK

=Max
TMC2242A,B 150 mA
TMC2242A-1,B-1 195 mA
TMC2242A-2,B-2 290 mA

Power Supply Current,
Unloaded

V

= Max, OE

DD

= HIGH, f

CLK

=Max
TMC2242A,B 120 mA
TMC2242A-1,B-1 155 mA
TMC2242A-2,B-2 230 mA

Power Supply Current,

V

= Max, CLK = LOW 5 mA

DD

Quiescent
I/O Pin Capacitance 5 pF

PIN

Input Current, HIGH V
Input Current, LOW V
Leakage Current, HIGH OE
Leakage Current, LOW OE
Short-Circuit Current VDD = Max, Output = HIGH, one pin to

= Max, V

DD

= Max, V

DD

= HIGH, V
= HIGH, V

= V

IN

DD

= 0 V

IN

= V

OUT
OUT

DD

= 0 V ±10 mA

-20 -80 mA

ground, one second duration max.

Output Voltage, HIGH SO15-0, IOH = Max 2.4 V

OH

Output Voltage, LOW SO15-0, IOL = Max 0.4 V

OL

±

10

±

10

±

10

m

A

m

A

m

A

Switching Characteristics

Parameter Conditions Min Typ Max Units

t

DO

t

HO

t

ENA

t

DIS

Output Delay Time C
Output Hold Time C
Output Enable Time C
Output Disable Time C

= 25 pF 15 ns

LOAD

= 25 pF 2.5 ns

LOAD

= 0 pF 12 ns

LOAD

= 0 pF 12 ns

LOAD

5