Fairchild Semiconductor SPT7850 Datasheet
SPT7850
10-BIT, 20 MSPS, 140 mW A/D CONVERTER
TECHNICAL DATA
JUNE 15, 2001
FEATURES
• Monolithic 20 MSPS converter
• 140 mW power dissipation
• On-chip track-and-hold
• Single +5 V power supply
• TTL/CMOS outputs
• 5 pF input capacitance
• Low cost
• Tri-state output buffers
• High ESD protection: 3,500 V minimum
• Selectable +3 V or +5 V logic I/O
GENERAL DESCRIPTION
The SPT7850 is a 10-bit monolithic, low-cost, ultralowpower analog-to-digital converter capable of minimum
word rates of 20 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the
need for external components. The input drive requirements are minimized due to the SPT7850’s low input
capacitance of only 5 pF.
Po wer dissipation is e xtremely lo w at only 140 mW typical
(165 mW maximum) at 20 MSPS with a power supply of
+5.0 V. The digital outputs are +3 V or +5 V, and are user
selectable. The SPT7850 is pin-compatible with an entire
APPLICATIONS
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
• IR imaging
• Scanners
• Digital communications
family of 10-bit, CMOS conv erters (SPT7835/40/50/55/60/
61), which simplifies upgrades. The SPT7850 has incorpo-
rated proprietary circuit design* and CMOS processing
technologies to achieve its adv anced perf ormance. Inputs
and outputs are TTL/CMOS-compatible to interface with
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7850 is available in 28-lead 300 mil PDIP and
32-lead small (7 mm square) TQFP packages over the
commercial temperature range, and in a 28-lead SOIC
package over the industrial temperature range.
*Patent pending
BLOCK DIAGRAM
and
1:8
Mux
P1
P2
.
.
.
P7
P8
A
CLK In
Enable
Data
Valid
Ref
IN
Timing
Control
In
ADC Section 1
T/H
ADC Section 2
ADC Section 7
ADC Section 8
T/H
Auto-
Zero
CMP
.
.
.
Auto-
Zero
CMP
Reference Ladder
11-Bit
SAR
DAC
11-Bit
SAR
11
DAC
11
11
11
.
.
.
V
REF
.
.
.
11
11
11-Bit
8:1
Mux/
Error
Correction
D10 Overrange
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD......................................................................+6 V
Output
Digital Outputs ...................................................10 mA
DVDD.....................................................................+6 V
Temperature
Input Voltages
Analog Input .............................. –0.5 V to AVDD +0.5 V
..............................................................0 to AV
V
REF
CLK Input ............................................................... V
AVDD – DVDD..................................................±100 mV
AGND – DGND ..............................................±100 mV
DD
DD
Operating T emper ature ............................ –40 to 85 °C
Junction Temperature ........................................ 175 °C
Lead Temperature, (soldering 10 seconds) ....... 300 °C
Storage Temperature............................ –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA=T
to T
MIN
, AVDD=DVDD=OVDD=+5.0 V , VIN=0 to 4 V, ƒ
MAX
TEST TEST SPT7850
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Resolution 10 Bits
DC Accuracy 100 kHz clock rate
Integral Linearity Error (ILE) V ±1.0 LSB
Differential Linearity Error (DLE) V ±0.5 LSB
No Missing Codes VI Guaranteed
Analog Input
Input Voltage Range VI V
Input Resistance IV 50 kΩ
Input Capacitance V 5.0 pF
Input Bandwidth (Small Signal) V 100 MHz
Offset V ±2.0 LSB
Gain Error V ±2.0 LSB
=40 MHz, ƒS=20 MSPS, V
CLK
1
RHS
RLS
=4.0 V , V
=0.0 V, unless otherwise specified.
RLS
V
RHS
V
Reference Input
Resistance VI 400 500 600 Ω
Bandwidth V 100 150 MHz
Voltage Range
IV 0 2.0 V
IV 3.0 AV
DD
V 1.0 4.0 5.0 V
V
∆(V
∆(V
V
V
V
RHF
RLS
RLS
RHS
RHS
– V
RLS
– V
)V90mV
RHS
– V
)V75mV
RLF
Reference Settling Time
V
RHS
V
RLS
V 15 Clock Cycles
V 20 Clock Cycles
Conversion Characteristics
Maximum Conversion Rate VI 20 MHz
Minimum Conversion Rate V 50 kHz
Pipeline Delay (Latency) IV 12 Clock Cycles
Aperture Delay Time V 5 ns
Aperture Jitter Time V 30 ps (p-p)
Dynamic Performance
Effective Number of Bits (ENOB)
= 3.58 MHz VI 8.8 Bits
ƒ
IN
= 10.3 MHz VI 8.5 Bits
ƒ
IN
Signal-to-Noise Ratio (SNR)
(without Harmonics)
= 3.58 MHz VI 53 56 dB
ƒ
IN
ƒIN = 10.3 MHz VI 52 55 dB
1
SPT7850SCN is screened for DC accuracy tests at 100 kHz. SPT7850SIS and SPT7850SCT are screened f or DC accuracy tests at 35 MHz.
SPT7850
2 6/15/01
ELECTRICAL SPECIFICATIONS
TA=T
to T
MIN
, AVDD=DVDD=OVDD=+5.0 V , VIN=0 to 4 V, ƒ
MAX
TEST TEST SPT7850
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Dynamic Performance
Total Harmonic Distortion (THD)
= 3.58 MHz VI 56 59 dB
ƒ
IN
= 10.3 MHz VI 53 56 dB
ƒ
IN
Signal-to-Noise and Distortion
(SINAD)
= 3.58 MHz VI 52 55 dB
ƒ
IN
ƒ
= 10.3 MHz VI 50 53 dB
IN
Spurious Free Dynamic Range ƒ
= 1 MHz V 63 dB
IN
Digital Inputs
Logic 1 Voltage VI 2. 0 V
Logic 0 Voltage VI 0.8 V
Maximum Input Current Low VI –10 +10 µA
Maximum Input Current High VI –10 +10 µA
Input Capacitance V 5 pF
=40 MHz, ƒS=20 MSPS, V
CLK
RHS
=4.0 V , V
=0.0 V, unless otherwise specified.
RLS
Digital Outputs
Logic 1 Voltage I
Logic 0 Voltage I
t
RISE
t
FALL
Output Enable to Data Output Delay 20 pF load, T
= 0.5 mA VI 3. 5 V
OH
= 1.6 mA VI 0.4 V
OL
15 pF load V 10 ns
15 pF load V 10 ns
= +25 °CV 10 ns
A
50 pF load over temp. V 22 ns
Power Supply Requirements
Voltages OV
DV
AV
Currents AI
DI
DD
DD
DD
DD
DD
IV 3.0 5.25 V
IV 4.75 5.0 5.25 V
IV 4.75 5.0 5.25 V
VI 10 12 mA
VI 18 21 mA
Power Dissipation VI 140 165 mW
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL TEST PROCEDURE
I 100% production tested at the specified temperature.
II 100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V Parameter is a typical value for information pur poses only.
VI 100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7850
3 6/15/01
SPECIFICATION DEFINITIONS
APERTURE DELAY
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
SINAD – 1.76
N =
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input
stage.
DIFFERENTIAL LINEARITY ERROR (DLE)
Error in the width of each code from its theoretical value.
(Theoretical = VFS/2N)
INTEGRAL LINEARITY ERROR (ILE)
Linearity error refers to the deviation of each individual
code (normalized) from a straight line drawn from –FS
through +FS. The deviation is measured from the edge of
each particular code to the true straight line.
6.02
OUTPUT DELAY
Time between the clock’s triggering edge and output data
valid.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy
after an analog input signal 125% of full scale is reduced
to 50% of the full-scale value.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the fundamental sinusoid power to the total
noise power. Harmonics are excluded.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
The ratio of the fundamental sinusoid power to the total
noise and distortion power.
TOTAL HARMONIC DISTORTION (THD)
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
SPT7850
4 6/15/01