Fairchild Semiconductor SPT7721 Datasheet

SPT7721

8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS

TECHNICAL DATA

NOVEMBER 8, 2001

FEATURES

• TTL/CMOS/PECL compatib le

• High conversion rate: 250 MSPS

• Single +5 V pow er supply

• V ery low pow er dissipation: 310 mW

• Po wer-down mode

• +3.0 V/+5.0 V (LVCMOS) digital output logic
compatibility

• Demuxed output ports

GENERAL DESCRIPTION

The SPT7721 is a high-speed, 8-bit analog-to-digital con­verter implemented in an advanced BiCMOS process. An
advanced folding and interpolating architecture provides
both a high conversion rate and v ery low power dissipation
of only 310 mW. The analog inputs can be operated in
either single-ended or differential input mode. A 2.5 V com­mon mode reference is provided on chip for the single­ended input mode to minimize external components.

BLOCK DIAGRAM

AGND DGND

AV

APPLICATIONS

• RGB video processing

• Digital communications

• High-speed instrumentation

• Projection display systems

The SPT7721 digital outputs are demuxed (double-wide)
with both dual-channel and single-channel selectable out­put modes. Demuxed mode supports either parallel
aligned or interleaved data output. The output logic is both
+3.0 V and +5.0 V compatible. The SPT7721 is av ailable in
a 44-lead TQFP surf ace mount package ov er the industrial
temperature range of –40 to +85 °C.

CC

OV

DD

V

IN

VIN

DA0DA

+

8-Bit

7

250 MSPS

ADC

CLK CLK

Common Mode

Voltage

Reference

+2.5 V

V

CM

PD CLK

CLK

Data Output Latches

Data Output

Mode Control

22

Reset

Reset

DMODE

&

DB0DB

DCLK

DCLK

1,2

7

OUT

OUT

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C

Supply V oltages

AVCC...................................................................... +6 V

OVDD..................................................................... +6 V

Input V oltages

Analog Inputs ............................... –0.5 V to VCC +0.5 V

Digital Inputs ................................ –0.5 V to V

+0.5 V

CC

T emperatures

Operating Temperature ........................... –40 to +85 °C

Storage Temper ature............................ –65 to +125 °C

Note: Operation at any Absolute Maximum Rating is not implied.

See Electrical Specifications for proper applied conditions in
typical applications.

ELECTRICAL SPECIFICATIONS

TA = T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Resolution 8 Bits
DC Performance ƒIN = 1 kHz

Analog Input

to T

, AV

MIN

MAX

= +5.0 V, ƒ

CC

= 250 MHz, VCM = 2.5 V, OVDD = 5.0 V, unless otherwise specified.

CLK

TEST TEST SPT7721

Differential Linearity Error (DLE) +25 °C V –0.70/+1.05 LSB

–40 °C to +85 °C V –0.95/+1.5 LSB

Integral Linearity Error (ILE) +25 °C V ±1.7 LSB

Best Fit –40 °C to +85 °C V ±2.25 LSB

No Missing Codes +25 °C, ƒ

= 1 kHz I Guaranteed

IN

Input V oltage Range

(with respect to V

–) +25 °C V ±470 mV

IN

P-P

Gain Variation VI 2 %
Input Common Mode (VCM) IV 2.3 2.5 3.0 V
Input Bias Current VI 10 µA
Input Resistance +25 °C V 50 kΩ
Input Capacitance +25 °C V 4 pF
Input Bandwidth +25 °C (–3 dB of FS) V 220 MHz
Offset Error VI ±10 mV
Offset Power Supply Rejection Ratio V 0.5 mV/V

Timing Characteristics

Maximum Conversion Rate VI 250 MSPS
Output Delay (Clock-to-Data) (t

) –40 °C to +85 °C IV 6 8 10.5 ns

pd1

Output Delay Tempco V 22 ps/°C
Aperture Delay Time (t

) IV 0.5 ns

ap

Aperture Jitter Time IV 2 ps rms
Pipeline Delay (Latency)

Single Channel Mode V 2.5 Clocks
Demuxed Interleaved Mode V 2.5 Clocks
Demuxed Parallel Mode

Channel B V 2.5 Clocks
Channel A V 3.5 Clocks

CLK to DCLK

Single Channel Mode (t
Dual Channel Mode (t

Delay Time

OUT

) IV467ns

pd2

) IV 5.3 6.16 7.8 ns

pd3

Dynamic Performance

Effective Number of Bits (ENOB)

= 70 MHz +25 °C VI 5.8 6.4 Bits

ƒ

IN

= 70 MHz –40 °C to +85 °C IV 5.5 6.0 Bits

ƒ

IN

Signal-to-Noise Ratio (SNR)

= 70 MHz +25 °C VI 42 43 dB

ƒ

IN

ƒIN = 70 MHz –40 °C to +85 °C IV 36 40 dB

SPT7721

2 11/8/01

ELECTRICAL SPECIFICATIONS

TA = T

MIN

to T

MAX

, AV

= +5.0 V, ƒ

CC

= 250 MHz, VCM = 2.5 V, OVDD = 5 V, unless otherwise specified.

CLK

TEST TEST SPT7721

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Dynamic Performance

Total Harmonic Distortion (THD)

= 70 MHz +25 °C VI –43 –40 dB

ƒ

IN

= 70 MHz –40 °C to +85 °C IV –42 –37 dB

ƒ

IN

Signal-to-Noise and Distortion (SINAD)

= 70 MHz +25 °C VI 3 7 40 dB

ƒ

IN

= 70 MHz –40 °C to +85 °C IV 35 38 dB

ƒ

IN

Power Supply Requirements

Voltage (Analog Supply) IV 4.75 5.0 5.25 V

AV

CC

OVDD Voltage (Digital Supply) IV 2.75 5.25 V

Current VI 62 70 mA

AV

CC

Power Dissipation with Inter nal Voltage Reference VI 310 3 50 mW

Common Mode Reference

Voltage VI 2.45 2.5 2.55 V
Voltage Tempco V 100 ppm/°C
Output Impedance I

= ±50 µA V 1 kΩ

OUT

Power Supply Rejection Ratio V 63 mV/V

Clock and Reset Inputs (Differential and Single-Ended)

Differential Signal Amplitude (V
Differential High Input Voltage (V
Differential Low Input Voltage (V

DIFF)

IHD)

ILD)

Differential Common-Mode Input (V
Single-Ended High Input Voltage (V
Single-Ended Low Input Voltage (V
Input Current High (II
Input Current Low (II

H)

L)

CMD)
IH)

IL)

VID = 1.5 V VI –100 20 +100 µA
VID = 1.5 V VI –100 20 +100 µA

VI 400 mV
IV 1.4 5 V
IV 0 3.9 V
IV 1.2 4.1 V
IV 1.8 V
IV 1.2 V

P-P

Power Down and Mode Control Inputs (Single-Ended)

High Input Voltage IV 2.0 AV

CC

V
Low Input Voltage IV 0 1.0 V
Maximum Input Current Low VI –100 10 +100 µA
Maximum Input Current High <4.0 V VI –100 10 +100 µA

Digital Outputs

Logic "1" Voltage I
Logic "0" Voltage I

OH
OL

TR/TF Data 10 pF load

OV
OV

TR/TF DCLK = (10 pF load)

OV
OVDD = 5 V V 0.7 ns

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

= –0.5 mA VI OVDD – 0.2 OVDD – 0.06 V

= +1.6 mA VI 0.13 0.2 V

= 3 V V 3.5 ns

DD

= 5 V V 2.0 ns

DD

= 3 V V 1.3 ns

DD

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

II 100% production tested at T

= +25 °C, and sample tested at the

A

specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-

zation data.

V Parameter is a typical value for information purposes only.

VI 100% production tested at TA = +25 °C. Parameter is guaranteed

over specified temperature range.

SPT7721

3 11/8/01

TYPICAL PERFORMANCE CHARACTERISTICS

AC Perf ormance vs Temperature

60

55

50

45

40

35

SFDR, THD, SNR, SINAD (dB)

30

40

75

70

65

(mA)

60

CC

AV

55

20

0

20

Temperature (°C)

AV

Current vs Temperature

CC

IN = 70 MHz

40

60 80

SFDR

THD
SNR

SINAD

100

AC P erf ormance vs Sample Rate

60

55

IN = 70 MHz

50

45

40

35

SFDR, SNR, THD, SINAD (dB)

30

0

50

100

150

200

Sample Rate (MSPS)

AVCC Current Power Do wn vs Temperature

3.0

2.8

2.6

(mA)

CC

2.4

AV

SFDR

SNR

THD

SINAD

250 300

50

45

6.0

4.0

2.0

0.0

mV

2.0

4.0

6.0

2.2

40

20

0

20

40

Temperature (°C)

60 80

100

2.0
40

20

0

20

40

Temperature (°C)

V olta ge Offset Error vs Temperature Percent Gain Error vs Temperature

1.06

1.05

1.04

1.03

%

1.02

1.01

40

20

0

20

40

Temperature (°C)

60 80

100

1.00
40

20

0

20

40

Temperature (°C)

60 80

60 80

100

100

SPT7721

4 11/8/01