Fairchild Semiconductor SI6435DQ Datasheet

Si6435DQ

30V P-Channel PowerTrench



MOSFET

Si6435DQ

September 2001

General Description

This P-Channel MOSFET is a rugged gate version of
Fairchild Semiconductor’s advanced PowerTrench
process. It has been optimized for power management
applications requiring a wide range of gate drive voltage
ratings (4.5V – 20V).

Applications

• Battery protection

• DC/DC conversion

Features

• –4.5 A, –30 V R
R

• Extended V

GSS

• High performance trench technology for extremely
low R

DS(ON)

• Low profile TSSOP-8 package

= 40 mΩ @ VGS = –10 V

DS(ON)

= 70 mΩ @ VGS = –4.5 V

DS(ON)

range (±20V) for battery applications

• Power management

• Load switch

D

S

S

D

G

S

S

D

TSSOP-8

Pin 1

Absolute Maximum Ratings T

=25oC unless otherwise noted

A

5
6
7
8

4
3
2
1

Symbol Parameter Ratings Units

V

DSS

V

GSS

I

D

P

D

TJ, T

STG

Drain-Source Voltage –30 V
Gate-Source Voltage

± 20

Drain Current – Continuous (Note 1) –4.5 A

– Pulsed –30

Power Dissipation (Note 1a) 1.3 W

(Note 1b)

0.6

Operating and Storage Junction Temperature Range –55 to +150

V

°C

Thermal Characteristics

R

θJA

Thermal Resistance, Junction-to-Ambient (Note 1a) 87

(Note 1b)

114

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

6435 Si6435DQ 13’’ 16mm 3000 units

2001 Fairchild Semiconductor Corporation

°C/W

Si6435DQ Rev B(W)

Si6435DQ

Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics

BV

DSS

∆BVDSS
∆T

J

I

DSS

I

GSSF

I

GSSR

Drain–Source Breakdown Voltage
Breakdown Voltage Temperature

Coefficient

= 0 V, ID = –250 µA

V

GS

I

= –250 µA, Referenced to 25°C

D

Zero Gate Voltage Drain Current VDS = –24 V, VGS = 0 V –1
Gate–Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –20 V, VDS = 0 V –100 nA

–30 V

–23

mV/°C

µA

On Characteristics (Note 2)

V

GS(th)

∆VGS(th)
∆T

J

R

DS(on)

I

D(on)

g

FS

Gate Threshold Voltage
Gate Threshold Voltage

Temperature Coefficient
Static Drain–Source

On–Resistance

= VGS, ID = –250 µA

V

DS

I

= –250 µA, Referenced to 25°C

D

VGS = –10 V, ID = –4.5 A

= –4.5 V, ID = –3.4 A

V

GS

= –10 V, ID = –4.5A, TJ=125°C

V

GS

On–State Drain Current VGS = –10 V, VDS = –5 V –30 A
Forward Transconductance VDS = –15 V, ID = –4.5 A 12 S

–1 –1.7 –3 V

5

27
42
38

40
70
60

mV/°C

mΩ

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance 854 pF
Output Capacitance 215 pF
Reverse Transfer Capacitance

= –15 V, V

V

DS

f = 1.0 MHz

GS

= 0 V,

112 pF

Switching Characteristics (Note 2)

t
t
t
t
t

Q
Q
Q

d(on)

r

d(off)

f

rr

g

gs

gd

Turn–On Delay Time 9 20 ns
Turn–On Rise Time 14 20 ns

= –15 V, ID = –1 A,

V

DD

= –10 V, R

V

GS

GEN

= 6 Ω

Turn–Off Delay Time 29 55 ns
Turn–Off Fall Time

V

Reverse Recovery Time

Total Gate Charge 15 35 nC
Gate–Source Charge 2.4 nC

= 0 V, IF = –1.25 A,

GS

/dt = 100A/µs

dI

F

V

= –15 V, ID = –4.5 A,

DS

= –10 V

V

GS

Gate–Drain Charge

15 25 ns
19 80 ns

3nC

Drain–Source Diode Characteristics and Maximum Ratings

I

S

V

SD

Maximum Continuous Drain–Source Diode Forward Current –1.25 A
Drain–Source Diode Forward

VGS = 0 V, IS = –1.25 A (Note 2) –0.75 –1.2 V

Voltage

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of

θJA

the drain pins. R

a) R
b) R

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%

is guaranteed by design while R

θJC

is 87 °C/W (steady state) when mounted on a 1 inch² copper pad on FR-4.

θJA

is 114 °C/W (steady state) when mounted on a minimum copper pad on FR-4.

θJA

is determined by the user's board design.

θCA

Si6435DQ Rev B(W)