Fairchild Semiconductor SI4925DY Datasheet

January 2001

Si4925DY



Dual P-Channel, Logic Level, PowerTrench

General Description Features

These P-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize the
on-state resistance and yet maintain low gate charge for
superior switching performance.

These devices are well suited for notebook computer
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.

MOSFET

-6 A, -30 V. R
R

Low gate charge (14.5nC typical).
High performance trench technology for extremely low

R

.

DS(ON)

High power and current handling capability.

= 0.032 Ω @ VGS = -10 V,

DS(ON)

= 0.045 Ω @ VGS = -4.5 V.

DS(ON)

SOT-23

SuperSOT

TM

-6

SuperSOT

TM

-8

SO-8 SOT-223

SOIC-16

D2

D2

D1

D1

SO-8

4925

pin1

G1

S1

Absolute Maximum Ratings T

G2

S2

= 25oC unless otherwise noted

A

5

6

7

8

Symbol Parameter Si4925DY Units

V

DSS

V

GSS

I

D

Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) -6 A

- Pulsed -20

P

T

J,TSTG

D

Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation

(Note 1b) 1
(Note 1c) 0.9

(Note 1a) 1.6

Operating and Storage Temperature Range -55 to 150 °C

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

4

3
2

1

© 2001 Fairchild Semiconductor International

Si4925DY Rev.A

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV

DSS

∆BV

DSS

I

DSS

I

GSSF

I

GSSR

ON CHARACTERISTICS

V

GS(th)

∆V

GS(th)

R

DS(ON)

Drain-Source Breakdown Voltage VGS = 0 V, I D = -250 µA -30 V
Breakdown Voltage Temp. Coefficient

/∆T

J

Zero Gate Voltage Drain Current

I

= -250 µA, Referenced to 25 oC

D

V

= -24 V, V

DS

= 0 V

GS

= 55°C

T

J

-21

-1 µA

Gate - Body Leakage, Forward VGS = 16 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

(Note 2)

V

= -16 V, V

GS

= 0 V

DS

Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.7 -3 V
Gate Threshold Voltage Temp. Coefficient

/∆T

J

Static Drain-Source On-Resistance

I

= 250 µA, Referenced to 25 oC

D

V

= -10 V, I D = -6 A

GS

4

0.025 0.032

mV/oC

-10 µA

-100 nA

mV/oC

Ω

TJ =125°C 0.033 0.051

0.034 0.045

16 S

I
g

D(ON)

FS

= -4.5 V, I D = -5 A

V

GS

On-State Drain Current VGS = -10 V, VDS = -5 V -20 A
Forward Transconductance

V

= -10 V, I D = -6 A

DS

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

SWITCHING CHARACTERISTICS

t

D(on)

t

r

t

D(off)

t

f

Q

g

Q

gs

Q

gd

Input Capacitance VDS = -15 V, VGS = 0 V,
Output Capacitance 400 pF

f = 1.0 MHz

1540 pF

Reverse Transfer Capacitance 170 pF

(Note 2)

Turn - On Delay Time
Turn - On Rise Time

V

= -15 V, I D = -1 A

DS

V

= -10 V, R

GEN

GEN

= 6 Ω

13 24 ns
22 35 ns

Turn - Off Delay Time 47 75 ns
Turn - Off Fall Time 18 30 ns
Total Gate Charge VDS = -10 V, I D = -6 A, 14.5 20 nC
Gate-Source Charge

V

= -5 V

GS

4 nC

Gate-Drain Charge 5 nC

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1.R
design while R

JA

θ

Maximum Continuous Drain-Source Diode Forward Current -1.3 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design.

CA

θ

(Note 2) -0.73 -1.2 V

is guaranteed by

JC

θ

a. 78OC/W on a 0.5 in

pad of 2oz copper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

2

b. 125OC/W on a 0.02 in

pad of 2oz copper.

2

c. 135OC/W on a 0.003 in

pad of 2oz copper.

2

Si4925DY Rev.A