Fairchild Semiconductor SI4920DY Datasheet

January 2001

Si4920DY
Dual N-Channel, Logic Level, PowerTrench

General Description Features

These N-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's
advanced PowerTrench process that has been
especially tailored to minimize the on-state
resistance and yet maintain superior switching
performance.

These devices are well suited for low voltage and
battery powered applications where low in-line
power loss and fast switching are required.



MOSFET

6 A, 30 V. R
R

= 0.028 Ω @ VGS = 10 V

DS(ON)

= 0.035 Ω @ VGS = 4.5 V.

DS(ON)

Fast switching speed.
Low gate charge (typical 9 nC).

High performance trench technology for extremely low
R

.

DS(ON)

High power and current handling capability.

SOT-23

SuperSOT

TM

-6

SuperSOT

TM

-8

SO-8 SOT-223

SOIC-16

D2

D2

5

4

D1

D1

4920

G2

6

7

3
2

S2

SO-8

pin1

S1

Absolute Maximum Ratings T

G1

= 25oC unless other wise noted

A

8

Symbol Parameter Si4920DY Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 6 A

- Pulsed 20

P

T

D

J,TSTG

Power Dissipation for Single Operation (Note 1a) 2 W

(Note 1b) 1.6
(Note 1c) 0.9

Operating and Storage Temperature Range -55 to 150 °C

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

1

© 2001 Fairchild Semiconductor International

Si4920DY Rev.A

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV

DSS

∆BV

DSS

I

DSS

I

GSSF

I

GSSR

ON CHARACTERISTICS

V

GS(th)

∆V

GS(th)

R

DS(ON)

Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 30 V
Breakdown Voltage Temp. Coefficient

/∆T

J

Zero Gate Voltage Drain Current

I

= 250 µA, Referenced to 25 oC

D

V

= 24 V, V

DS

= 0 V

GS

= 55°C

T

J

23

1 µA

Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

(Note 2)

V

= -20 V, V

GS

= 0 V

DS

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 3 V
Gate Threshold Voltage Temp. Coefficient

/∆T

J

Static Drain-Source On-Resistance

I

= 250 µA, Referenced to 25 oC

D

V

= 10 V, I D = 6 A

GS

-4

0.023 0.028

mV /oC

10 µA

-100 nA

mV /oC

TJ =125°C 0.036 0.044

0.029 0.035

18 S

I
g

D(ON)

FS

= 4.5 V, I D = 5 A

V

GS

On-State Drain Current VGS = 10 V, VDS = 5 V 20 A
Forward Transconductance

V

= 15 V, I D= 6 A

DS

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

SWITCHING CHARACTERISTICS

t

D(on)

t

r

t

D(off)

t

f

Q

g

Q

gs

Q

gd

Input Capacitance VDS = 15 V, VGS = 0 V,
Output Capacitance 185 pF

f = 1.0 MHz

830 pF

Reverse Transfer Capacitance 80 pF

(Note 2)

Turn - On Delay Time
Turn - On Rise Time

V

= 15 V, I D = 1 A

DS

V

= 10 V , R

GS

GEN

= 6 Ω

6 12 ns

10 18 ns

Turn - Off Delay Time 18 29 ns
Turn - Off Fall Time 5 12 ns
Total Gate Charge VDS = 15 V, I D = 7.5 A, 9 13 nC
Gate-Source Charge

V

= 5 V

GS

2.8 nC

Gate-Drain Charge 3.1 nC

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

Notes:

1. R

SD

JA

θ

design while R

Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design.

CA

θ

V

= 0 V, IS = 1.3 A

GS

(Note 2)

0.73 1.2 V

is guaranteed by

JC

θ

Ω

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width <

300µs, Duty Cycle < 2.0%.

a. 78OC/W on a 0.5 in

pad of 2oz copper.

2

b. 125OC/W on a 0.02 in

pad of 2oz copper.

2

c. 135OC/W on a 0.003 in

pad of 2oz copper.

2

Si4920DY Rev.A