Fairchild Semiconductor SI4539DY Datasheet

Si4539DY

Si4539DY
Dual N & P-Channel Enhancement Mode Field Effect Transistor

General Description Features

These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.

TM

SuperSOT

-6

N-Channel 7.0 A,30 V, R
R
P-Channel -5.0 A,-30 V,R
R

=0.028 Ω @ VGS=10 V

DS(ON)

=0.040 Ω @ VGS= 4.5 V.

DS(ON)

=0.052 Ω @ VGS=-10 V

DS(ON)

=0.080Ω @ VGS=-4.5 V.

DS(ON)

High density cell design for extremely low R
High power and current handling capability in a widely used

surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.

January 2001

.

DS(ON)

SOIC-16SOT-23 SuperSOTTM-8 SO-8 SOT-223

D2

D2

5

D1

D1

4539

6

7

3
2

G2

SO-8

pin 1

S1

G1

S2

8

141

T

Absolute Maximum Ratings

Symbol Parameter N-Channel P-Channel Units

V

DSS

V

GSS

I

D

P

D

T

J,TSTG

THERMAL CHARACTERISTICS

R

θJA

R

θ

JC

Drain-Source Voltage 30 -30 V
Gate-Source Voltage 20 -20 V
Drain Current - Continuous (Note 1a) 7 -5 A

- Pulsed 20 -20
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation

Operating and Storage Temperature Range -55 to 150 °C

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

= 25°C unless otherwise noted

A

(Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9

© 2001 Fairchild Semiconductor International

Si4539DY Rev. A

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS

BV

DSS

∆BV

DSS

I

DSS

I

GSSF

I

GSSR

ON CHARACTERISTICS

V

GS(th)

∆V

GS(th)

R

DS(ON)

I

D(on)

g

FS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V

= 0 V, ID = -250 µA

V

GS

Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC N-Ch 30 mV/oC

/∆T

J

= -250 µA, Referenced to 25 oC

I

D

Zero Gate Voltage Drain Current VDS = 24 V, V

= -24 V, V

V

DS

= 0 V N-Ch 1 µA

GS

= 0 V

GS

P-Ch -30 V

P-Ch -25

P-Ch -1 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
Gate - Body Leakage, Reverse

(Note 2)

Gate Threshold Voltage

Gate Threshold Voltage Temp. Coefficient

/∆T

J

Static Drain-Source On-Resistance

On-State Drain Current

Forward Transconductance

V

= -20 V, VDS = 0 V

GS

V

= VGS, ID = 250 µA

DS

= VGS, ID = -250 µA

V

DS

I

= 250 µA, Referenced to 25 oC

D

= -250 µA, Referenced to 25 oC

I

D

V

= 10 V, ID = 7.0 A

GS

V

= 4.5 V, ID = 6.0 A 0.035 0.04

GS

= -10 V, ID = -5.0 A

V

GS

= -4.5 V, ID = - 4.0 A 0.068 0.08

V

GS

V

= 10 V, V

GS

= -10 V, V

V

GS

V

= 5 V, I D = -7 A

DS

= -5 V, I D = -5 A P-Ch 8 S

V

DS

= 5 V

DS

= -5 V P-Ch -20

DS

All -100 nA

N-Ch 1 1.7 3 V

P-Ch -1 -1.5 -3 V

N-Ch -4.4

P-Ch 3.2

N-Ch 0.024 0.028

P-Ch 0.044 0.052

N-Ch 20 A

N-Ch 15 S

mV/oC

Ω

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance

Input Capacitance N-Ch 345 pF

Reverse Transfer Capacitance N-Ch 90 pF

V

= 15 V, VGS = 0 V,

DS

f = 1.0 MHz

= -15 V, VGS = 0 V,

V

DS

f = 1.0 MHz

N-Ch 650 pF

P-Ch 730

P-Ch 400

P-Ch 90

Si4539DY

Si4539DY Rev. A

Electrical Characteristics (continued)

SWITCHING CHARACTERISTICS
Symbol Parameter Conditions Type Min Typ Max Units

t

t

t

t

Q

Q

Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time V

Turn - On Rise Time N-Ch 14 25 ns

Turn - Off Delay Time V

Turn - Off Fall Time N-Ch 9 18 ns

Total Gate Charge

Gate-Source Charge N-Ch 3.2 nC

Gate-Drain Charge

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R

JA

θ

design while R

Maximum Continuous Drain-Source Diode Forward Current N-Ch 1.3 A

Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design.

CA

θ

(Note 2)

= 10 V, I D = 1 A N-Ch 8 16 ns

DS

= 10 V , R

V

GS

GEN

= 6 Ω

P-Ch 11 20

P-Ch 10 18

= -10 V, I D = -1 A N-Ch 23 37 ns

DS

= -10 V , R

V

GS

GEN

= 6 Ω

P-Ch 90 125

P-Ch 55 80

V

= 10 V, I D = 7 A,

DS

= 10 V

V

GS

= -10 V, I D = -5 A, P-Ch 3.5

V

DS

V

= -10 V

GS

N-Ch 18 26 nC

P-Ch 19 27

N-Ch 4.3 nC

P-Ch 3.6

P-Ch -1.3 A

(Note 2) N-Ch 0.75 1.2 V

= 0 V, IS = -1.3 A

V

GS

(Note 2)

P-Ch -0.75 -1.2 V

is guaranteed by

JC

θ

Si4539DY

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width <

300µs, Duty Cycle < 2.0%..

a. 78OC/W on a 0.5 in

pad of 2oz copper.

2

b. 125OC/W on a 0.02 in

pad of 2oz copper.

2

c. 135OC/W on a 0.003 in

pad of 2oz copper.

2

Si4539DY Rev. A