Fairchild Semiconductor SI3457DV Datasheet
Si3457DV
Single P-Channel Logic Level PowerTrench
MOSFET
Si3457DV
April 2001
PRELIMINARY
General Description
This P-Channel Logic Level MOSFET is produced
using Fairchild’s advanced PowerTrench process. It
has been optimized for battery power management
applications.
Applications
• Battery management
• Load switch
• Battery protection
Features
• –4 A, –30 V. R
R
• Low gate charge
• High performance trench te chnology for extremely
low R
DS(ON)
= 50 mΩ @ VGS = –10 V
DS(ON)
= 75 mΩ @ VGS = –4.5 V
DS(ON)
S
D
D
1
2
6
5
G
SuperSOT -6
TM
D
D
Absolute Maximum Ratings T
o
=25
C unless otherwise noted
A
3
4
Symbol Parameter Ratings Units
V
Drain-Source Voltage –30 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1a) –4 A
– Pulsed –20
Maximum Power Dissipation (Note 1a) 1.6 W PD
TJ, T
Operating and Storage Junction Temperature Range –55 to +150
STG
(Note 1b)
±25
0.8
V
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 78
(Note 1) 30
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
.457 Si3457DV 7’’ 8mm 3000 units
2001 Fairchild Semiconductor Corporation
°C/W
°C/W
Si3457DV Rev A (W)
Si3457DV
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
∆BVDSS
∆T
I
Zero Gate Voltage Drain Current VDS = –24 V, VGS = 0 V –1
DSS
I
GSSF
I
GSSR
Breakdown Voltage Temperature
Coefficient
J
Gate–Body Leakage, Forward VGS = 25 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –25 V VDS = 0 V –100 nA
V
= 0 V, ID = –250 µA
GS
= –250 µA,Referenced to 25°C
I
D
–30 V
–22
mV/°C
µA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
I
On–State Drain Current VGS = –10 V, VDS = –5 V –20 A
D(on)
V
= VGS, ID = –250 µA
DS
= –250 µA,Referenced to 25°C
I
D
VGS = –10 V, ID = –4 A
V
= –4.5 V, ID = –3.4 A
GS
= –10 V, ID = –4 A;TJ=125°
V
GS
–1 –1.8 –3 V
4
44
67
60
50
75
70
mV/°C
mΩ
gFS Forward Transconductance VDS = –5 V, ID = –4 A 8.4 S
Dynamic Characteristics
C
Input Capacitance 470 pF
iss
C
Output Capacitance 126 pF
oss
C
Reverse Transfer Capacitance
rss
= –15 V, V
V
DS
f = 1.0 MHz
= 0 V,
GS
61 pF
Switching Characteristics (Note 2)
t
Turn–On Delay Time 7 14 ns
d(on)
tr Turn–On Rise Time 12 22 ns
t
Turn–Off Delay Time 16 29 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 6 8.1 nC
Qgs Gate–Source Charge 2.1 nC
Qgd Gate–Drain Charge
= –15 V, ID = –1 A,
V
DD
= –10 V, R
V
GS
= –15 V, ID = –4 A,
V
DS
V
= –.5 V
GS
GEN
= 6 Ω
6 12 ns
2 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current –1.3 A
VSD Drain–Source Diode Forward
Voltage
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
is guaranteed by design while R
θJC
is determined by the user's board design.
θCA
a) 78°C/W when
mounted on a 1in
of 2 oz copper
VGS = 0 V, IS = –1.3 A (Note 2) –0.77 –1.2 V
2
pad
b) 156°C/W when mounted
on a minimum pad of 2 oz
copper
Si3457DV Rev A(W)
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