Fairchild Semiconductor SI3454DV Datasheet
October 2001
Si3454DV
N-Channel PowerTrench
MOSFET
Si3454DV
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced Power
Trench process that has been especially tailored to
minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
• 4.2 A, 30 V. R
R
• High performance trench technology for extremely
low R
• Low gate charge (9.4 nC typical)
• High power and current handling capability
DS(ON)
= 65 mΩ @ VGS = 10 V
DS(ON)
= 95 mΩ @ VGS = 4.5 V
DS(ON)
S
D
D
1
2
6
5
G
SuperSOT -6
TM
D
D
Absolute Maximum Ratings T
o
=25
C unless otherwise noted
A
3
4
Symbol Parameter Ratings Units
V
Drain-Source Voltage 30 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1a) 4.2 A
– Pulsed 20
Maximum Power Dissipation (Note 1a) 1.6 W PD
TJ, T
Operating and Storage Junction Temperature Range -55 to +150
STG
(Note 1b)
±20
0.8
V
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 78
(Note 1) 30
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
.454 Si3454DV 7’’ 8mm 3000 units
2001 Fairchild Sem iconductor Corporation
°C/W
°C/W
Si3454DV Rev A
Si3454DV
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
∆BVDSS
∆T
I
Zero Gate Voltage Drain Current VDS = 30 V, VGS = 0 V 1
DSS
Breakdown Voltage Temperature
Coefficient
J
I
Gate–Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
GSSF
I
Gate–Body Leakage, Reverse VGS = –20 V, VDS = 0 V –100 nA
GSSR
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
= 30 V, VGS = 0 V, TJ=70°C
V
DS
30 V
20
mV/°C
µA
25
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
I
On–State Drain Current VGS = 10 V, VDS = 5 V 15 A
D(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
= VGS, ID = 250 µA
V
DS
I
= 250 µA, Referenced to 25°C
D
= 10 V, ID = 4.2 A
V
GS
V
= 4.5 V, ID = 3.4 A
GS
gFS Forward Transconductance VDS = 10 V, ID = 4.2 A 10 S
1 1.5 2 V
– 4
33
44
65
95
mV/°C
mΩ
Dynamic Characteristics
C
Input Capacitance 460 pF
iss
C
Output Capacitance 115 pF
oss
C
Reverse Transfer Capacitance
rss
= 15 V, V
V
DS
f = 1.0 MHz
= 0 V,
GS
45 pF
Switching Characteristics (Note 2)
V
= 15 V, ID = 1 A,
t
Turn–On Delay Time 5 20 nS
d(on)
tr Turn–On Rise Time 8 30 nS
t
Turn–Off Delay Time 17 35 nS
d(off)
tf Turn–Off Fall Time
trr
Source-Drain Reverse Recovery
Time
Qg Total Gate Charge 9.4 15 nC
Qgs Gate–Source Charge 1.2 nC
Qgd Gate–Drain Charge
DS
= 10 V, R
V
GS
GEN
= 6 Ω
IF = 1.7 A, di/dt = 100 A/uS
V
= 10 V, ID = 4.2 A,
DS
V
= 10 V
GS
13 20 nS
80 nS
1.1 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current 1.7 A
VSD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the drain
θJA
pins. R
a. 78°C/W when mounted on a 1in
b. 156°C/W when mounted on a minimum pad.
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Drain–Source Diode Forward
Voltage
is guaranteed by design while R
θJC
2
pad of 2oz copper on FR-4 board.
= 0 V, IS = 1.7 A (Note 2) 1.2 V
V
GS
is determined by the user's board design.
θCA
Si3454DV Rev A
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