Fairchild Semiconductor RFP50N05L Datasheet

GATE

DRAIN (FLANGE)

SOURCE

DRAIN

RFG50N05L, RFP50N05L

Data Sheet January 2002

50A, 50V, 0.022 Ohm, Logic Level,
N-Channel Power MOSFETs

These are logic-level N-channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic-level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor relay
drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V - 5V range, thereby facilitating true on-off power
control directly from integrated circuit supply voltages.

Formerly developmental type TA09872.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG50N05L TO-247 RFG50N05L

RFP50N05L TO-220AB RFP50N05L

NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A.

Features

• 50A, 50V

•r

• UIS SOA Rating Curve (Single Pulse)

• Design Optimized for 5V Gate Drive

• Can be Driven Directly from CMOS, NMOS, TTL Circuits

• Compatible with Automotive Drive Requirements

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Majority Carrier Device

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.022 Ω

DS(ON)

Components to PC Boards”

Symbol

D

G

Packaging

DRAIN

(BOTTOM

SIDE METAL)

S

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

©2002 Fairchild Semiconductor Corporation RFG50N05L, RFP50N05L Rev. B

± 10 ±

µ

θ

θ

RFG50N05L, RFP50N05L

Absolute Maximum Ratings

o

T

= 25

C, Unless Otherwise Specified

C

RFG50N05L RFP50N05L UNITS

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20k Ω) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . V

GS

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Above T

o

= 25

C, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

DS

D

DM

GS

D

50 50 V

50 50 V

50

130

50

130

10 V

110

0.88

110

0.88

W/

A
A

W

o

C

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA Curve -

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

-55 to 150 -55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

300
260

o

C

o

C

o

C

NOTE:

J

= 25

o

C to 125

1. T

Electrical Specifications

o

C.

o

T

= 25

C, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV

Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

Drain to Source On Resistance (Note 2) r

DS(ON)

Turn-On Time t

Turn-On Delay Time t

D(ON)

Rise Time t

Turn-Off Delay Time t

D(OFF)

Fall Time t

Turn-Off Time t

Total Gate Charge Q

(OFF)

G(TOT)

Gate Charge at 5V Q

Threshold Gate Charge Q

Thermal Resistance Junction to Case R

Thermal Resistance Junction to Ambient R

DSS

GSS

(ON)

G(th

I

DSS

D

V

V

V

V

I

D

I

D

V
(Figures 12, 15, 16)

r

f

V

V

G(5)

)V

JC

JA

= 250 µ A, V

= V

GS

= Rated BV

DS

= 0.8 x Rated BV

DS

= ± 10V, V

GS

= 50A, V

= 50A, V

= 5V, R

GS

= 0V (Figure 10) 50 - - V

GS

, I

= 250 µ A (Figure 9) 1 - 2 V

DS

D

, V

DSS

= 0V - - ± 100 nA

DS

= 5V (Figure 7) - - 0.022 Ω

GS

= 4V - - 0.027 Ω

GS

= 2.5 Ω , R

GS

= 0 - - 25

GS

DSS

, V

= 1 Ω

L

GS

= 0, T

= 150

C

o

C - - 250 µ A

- - 100 ns

-15- ns

-50- ns

-50- ns

-15- ns

- - 100 ns

= 0 to 10V V

GS

= 0 to 5V - - 80 nC

GS

= 0 to 1V - - 6 nC

GS

= 40V, I

DD

R

L

= 0.8 Ω

D

(Figures 17, 18)

= 50A

- - 140 nC

- - 1.14

--80

o

o

A

C/W

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V

Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulsed: pulse duration = 300 µ s maximum, duty cycle = 2%.

3. Repititive rating: pulse width limited by maximum junction temperature.

©2002 Fairchild Semiconductor Corporation RFG50N05L, RFP50N05L Rev. B

I

= 50A - - 1.5 V

SD

I

= 50A, dI

SD

/dt = 100A/ µ s - - 1.25 ns

SD