Fairchild Semiconductor RFD14N05L, RFD14N05LSM, RFP14N05L Datasheet

G

D

S

GATE

SOURCE

DRAIN (FLANGE)

RFD14N05L, RFD14N05LSM, RFP14N05L

Data Sheet January 2002

14A, 50V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs

These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V-5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.

Formerly developmental type TA09870.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD14N05L TO-251AA 14N05L

RFD14N05LSM TO-252AA 14N05L

RFP14N05L TO-220AB FP14N05L

NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.

Features

• 14A, 50V

DS(ON)

= 0.100 Ω

®

Model

•r

• Temperature Compensating PSPICE

• Can be Driven Directly from CMOS, NMOS, and
TTL Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

• 175

C Operating Temperature

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

©2002 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B

± 10

µ

µ

±

Ω

θ

θ

θ

RFD14N05L, RFD14N05LSM, RFP14N05L

Absolute Maximum Ratings

o

T

= 25

C, Unless Otherwise Specified

C

RFD14N05L, RFD14N05LSM,

RFP14N05L UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20k Ω ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate above 25

o

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

DSS

DGR

GS

D

DM

AS

D

T

J,

STG

Refer to Peak Current Curve

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

50 V
50 V

14

Refer to UIS Curve

48

0.32

-55 to 175

300
260

W/

V
A

W

o

C

o

C

o

C

o

C

NOTE:

J

= 25

o

1. T

Electrical Specifications

C to 150

o

C.

o

T

= 25

C, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV

Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

Drain to Source On Resistance (Note 2) r

DS(ON)

Turn-On Time t

Turn-On Delay Time t

d(ON)

Rise Time t

Turn-Off Delay Time t

d(OFF)

Fall Time t

Turn-Off Time t

Total Gate Charge Q

(OFF)

g(TOT)

Gate Charge at 5V Q

Threshold Gate Charge Q

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Thermal Resistance Junction to Case R

Thermal Resistance Junction to Ambient R

R

DSS

GSS

(ON)

g(TH)

OSS

RSS

I

DSS

r

= 250 µ A, V

D

V

= V

GS

DS

V

= 40V, V

DS

V

= 40V, V

DS

V

= ± 10V - -

GS

I

= 14A, V

D

V

= 25V, I

DD

R

= 3.57 Ω , V

L

R

= 0.6 Ω

GS

= 0V, Figure 13 50 - - V

GS

, I

= 250 µ A, Figure12 1 - 2 V

D

= 0V - - 1

GS

= 0V, T

GS

= 5V, Figures 9, 11 - - 0.100

GS

= 7A,

D

= 5V,

GS

= 150

C

o

C--50

- - 60 ns

-13 - ns

-24 - ns

-42 - ns

f

-16 - ns

- - 100 ns

V

g(5)

ISS

= 0V to 10V V

GS

V

= 0V to 5V - - 25 nC

GS

V

= 0V to 1V - - 1.5 nC

GS

V

= 25V, V

DS

= 0V, f = 1MHz

GS

Figure 14

= 40V, I

DD

R

= 2.86 Ω

L

Figures 20, 21

= 14A,

D

- - 40 nC

- 670 - pF

- 185 - pF

-50 - pF

JC

TO-251 and TO-252 - - 100

JA

TO-220 - - 80

JA

- - 3.125

100 nA

o

C/W

o

C/W

o

C/W

A

A

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V

Diode Reverse Recovery Time t

NOTES:

2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

©2002 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B

SD

rr

I

= 14A - - 1.5 V

SD

I

= 14A, dI

SD

/dt = 100A/ µ s - - 125 ns

SD

8

4

0

25 50 75 100

125

150

12

I

D

, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

16

175

t, PULSE WIDTH (s)

10

10

-5

10

-4

10

-3

10

-2

10

-1

10

0

10

1

VGS = 10V

100

I

DM

, PEAK CURRENT CAPABILITY (A)

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

I = I

25

175 - T

C

150

FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 5V

200

TC = 25oC

RFD14N05L, RFD14N05LSM, RFP14N05L

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100

0

0

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

1

150

175

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

TEMPERATURE

100

10

, DRAIN CURRENT (A)

D

I

0.5

0.5

0.2

0.1

0.1

, NORMALIZED

JC

θ

Z

1

1

0.05

0.02

THERMAL IMPEDANCE

0.01

0.01

-5

10

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

SINGLE PULSE

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TJ = MAX. RATED

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

TC = 25oC

100µs

1ms

10ms

100ms

DC

100

-2

10

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

P

DM

t

1

t

2

1/t2

x R

JC

θ

0

10

+ T

JC

C

θ

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

©2002 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B