Fairchild Semiconductor RC5051M Datasheet

www.fairchildsemi.com

REV. 1.0.4 4/2/01

Features

• Programmable output from 1.3V to 3.5V using an
integrated 5-bit DAC

• 85% efficiency typical

• Adjustable operation from 80KHz to 1MHz

• Integrated Power Good and Enable functions

• Overvoltage protection

• Overcurrent protection

• Drives N-channel MOSFETs

• 20 pin SOIC package

• Meets Intel Pentium II specifications using minimum
number of external components

Applications

• Power supply for Pentium

®

II

• VRM for Pentium II processor

• Programmable step-down power supply

Description

The RC5051 is a synchronous mode DC-DC controller IC
which provides an accurate, programmable output voltage
for all Pentium II CPU applications. The RC5051 uses a
5-bit D/A converter to program the output voltage from 1.3V
to 3.5V. The RC5051 uses a high level of integration to
deliver load currents in excess of 19A from a 5V source with
minimal external circuitry. Synchronous-mode operation
offers optimum efficiency over the entire specified output
voltage range, and the internal oscillator can be programmed
from 80KHz to 1MHz for additional flexibility in choosing
external components. An on-board precision low TC refer­ence achieves tight tolerance voltage regulation without
expensive external components. The RC5051 also offers
integrated functions including Power Good, Output Enable,
over-voltage protection and current limiting.

Block Diagram

DIGITAL

CONTROL

+5V

1

16

20 19 18 17 8 2

3

9

7

12

13

4

5

–

+

1.24V

REFERENCE

5-BIT

DAC

65-5051-01

POWER

GOOD

OSC

PWRGD

VREF

VID0

VID1

VID2 VID4

VID3

ENABLE

–

+

–

+

–

+

+5V

VO

RC5051

+12V

RC5051

Programmable Synchronous DC-DC Controller for
Low Voltage Microprocessors

Pentium is a registered trademark of Intel Corporation.

RC5051 PRODUCT SPECIFICATION

2

REV. 1.0.4 4/2/01

Pin Assignments

Pin Definitions

Pin Number Pin Name Pin Function Description

1 CEXT Oscillator Capacitor Connection . Connecting an external capacitor to this pin sets

the internal oscillator frequency. Layout of this pin is critical to system performance.
See Application Information for details.

2 ENABLE Output Enable . A logic LOW on this pin will disable the output. An internal pull-up

resistor allows for either open collector or TTL compatibility.

3 PWRGD Power Good Flag . An open collector output that will be at logic LOW if the output

voltage is not within ± 12% of the nominal output voltage setpoint.

4 IFB

High Side Current Feedback . Pins 4 and 5 are used as the inputs for the current

feedback control loop. Layout of these traces is critical to system performance. See
Application Information for details.

5 VFB

Voltage Feedback . Pin 5 is used as the input for the voltage feedback control loop and

as the low side current feedback input. See Application Information for details regarding
correct layout.

6 VCCA Analog VCC . Connect to system 5V supply and decouple with a 0.1 µ F ceramic

capacitor.

7 VCCP Power VCC for low side FET driver . Connect to system 5V supply and place a 1 µ F

ceramic capacitor for decoupling and local charge storage.

8 VID4 VID4 Input . A logic 1 on this open collector/TTL input will enable the VID3–VID0 inputs

to set the output from 2.1V to 3.5V, and a logic 0 will set the output from 1.3V to 2.05V,
as shown in Table 1. Pullup resistors are internal to the controller.

9 LODRV Low Side FET Driver . Connect this pin to the gate of an N-channel MOSFET for

synchronous operation. The trace from this pin to the MOSFET gate should be < 0.5".

10, 11 GNDP Power Ground . Return pin for high currents flowing in pins 7 and 13 (VCCP and

VCCQP). Connect to a low impedance ground.

12 HIDRV High Side FET Driver . Connect this pin to the gate of an N-channel MOSFET. The

trace from this pin to the MOSFET gate should be < 0.5".

13 VCCQP Power VCC . For high side FET driver. VCCQP must be connected to a voltage of at

least VCCA + V

GS,ON

(MOSFET), and place a 1 µ F ceramic capacitor for decoupling

and local charge storage. See Application Information for details

14 GNDD Digital Ground . Return path for digital logic. Connect to a low impedance system

ground plane to minimize ground loops.

15 GNDA Analog Ground . Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

16 VREF Reference Voltage Test point . This pin provides access to the DAC output and should

be decoupled to ground using 0.1 µ F capacitor. No load should be connected.

17-20 VID0-VID3 Voltage Identification Code Inputs . These open collector/TTL compatible inputs will

program the output voltage over the ranges specified in Table 1. Pull-up resistors are
internal to the controller.

1

2

3

4

5

6

8

7

VID0

VID1

VID2

VID3

VREF

GNDA

VCCQP

GNDD

20

19

18

17

16

15

13

912

10 11

65-5051-02

14

CEXT

ENABLE

PWRGD

IFB

RC5051

VFB

VCCA

VID4

VCCP

GNDP

HIDRV

GNDP

LODRV

PRODUCT SPECIFICATION RC5051

REV. 1.0.4 4/2/01

3

Absolute Maximum Ratings

Operating Conditions

Electrical Specifications

(V

CCA

= 5V, V

OUT

= 2.8V, f

osc

= 300 KHz, and T

A

= +25 ° C using circuit in Figure 1, unless otherwise noted)

The • denotes specifications which apply over the full operating temperature range.

Notes:

1. Steady Date Voltage Regulation includes Initial Voltage Setpoint, Load Regulation, Output Ripple and Output Temperature Drift

and is measured at the converter’s output capacitors.

2. As measured at the converter’s output capacitors. For motherboard applications, the PCB layout should exhibit no more than

0.5m Ω trace resistance between the converter’s output capacitors and the CPU.

Supply Voltages, VCCA, VCCP, VCCQP to GND 13V
Supply Voltage VCCQP, Charge Pump (V

IN

+VCCA) 18V
Voltage Identification Code Inputs, VID4-VID0 13V
Junction Temperature, T

J

150 ° C
Storage Temperature -65 to 150 ° C
Lead Soldering Temperature, 10 seconds 300 ° C

Parameter Conditions Min. Typ. Max. Units

Supply Voltage, VCCA, VCCP 4.75 5 5.25 V
Input Logic HIGH 2.0 V
Input Logic LOW 0.8 V
Ambient Operating Temp 0 70

°

C
Output Driver Supply, VCCQP 8.5 12 V
PWRGD threshold Logic High

Logic Low

93
88

107
112

%V

OUT

%V

OUT

Parameter Conditions Min. Typ. Max. Units

Output Voltage See Table 1

•

1.3 3.5 V
Output Current 15 A
Initial Voltage Setpoint I

LOAD

= 0.8A, V

OUT

= 2.8V

V

OUT

= 2.0V

2.797

2.000

2.825

2.020

2.853

2.040

V
V

Output Temperature Drift T

A

= 0 to 70 ° CV

OUT

= 2.8V

V

OUT

= 2.0V

•

•

+16
+11

mV
mV

Load Regulation I

LOAD

= 0.8A to 14.2A

•

-20 mV

Line Regulation V

IN

= 4.75V to 5.25V

•±

2mV

Output Ripple 20MHz BW, I

LOAD

= 14.2A

±

13 mVpk

Total Output Variation
Steady State

1

V

OUT

= 2.8V

V

OUT

= 2.0V

•

•

2.740

1.940

2.900

2.060

V
V

Total Output Variation
Transient

2

I

LOAD

= 0.8 to 14.2A, V

OUT

= 2.8V

V

OUT

= 2.0V

•

•

2.670

1.900

2.930

2.100

V
V

Short Circuit Detect Threshold

•

100 120 140 mV

Efficiency I

LOAD

= 14.2A, V

OUT

= 2.8V

•

82 %
Output Driver Rise and Fall Time See Figure 2 80 nsec
Output Driver Deadtime 1 See Figure 2 5 %/f

OSC

Output Driver Deadtime 2 See Figure 2 80 nsec
Turn-on Response Time I

LOAD

= 0A to 14.2A 10 msec
Oscillator Range 80 1000 KHz
Oscillator Frequency C

EXT

= 100 pF 270 300 330 KHz

Max Duty Cycle 90 95 %

RC5051 PRODUCT SPECIFICATION

4

REV. 1.0.4 4/2/01

Table 1. Output Voltage Programming Codes

Note:

1. 0 = processor pin is tied to GND.
1 = processor pin is open.

VID4 VID3 VID2 VID1 VID0 V

OUT

to CPU

01111 1.30V

01110 1.35V

01101 1.40V

01100 1.45V

01011 1.50V

01010 1.55V

01001 1.60V

01000 1.65V

00111 1.70V

00110 1.75V

00101 1.80V

00100 1.85V

00011 1.90V

00010 1.95V

00001 2.00V

00000 2.05V

11111 No CPU

11110 2.1V

11101 2.2V

11100 2.3V

11011 2.4V

11010 2.5V

11001 2.6V

11000 2.7V

10111 2.8V

10110 2.9V

10101 3.0V

10100 3.1V

10011 3.2V

10010 3.3V

10001 3.4V

10000 3.5V

PRODUCT SPECIFICATION RC5051

REV. 1.0.4 4/2/01

5

Typical Operating Characteristics

(VCCA, VCCD = 5V, f

OSC

= 280 KHz, and T

A

= +25 ° C using circuit in Figure 1, unless otherwise noted)

Efficiency vs. Output Current

65-5050-03

80.0

78.0

76.0

74.0

72.0

70.0

82.0

84.0

86.0

88.0

135791113

V

OUT

= 2.8V

V

OUT

= 2.0V

14.5

Output Current (A)

Efficiency (%)

Load Regulation, V

OUT

= 2.8 V

2.77

2.76

2.75

2.74

2.73

2.78

2.79

2.80

2.81

2.82

2.83

1 3 5 7 9 11 13 14.5

Output Current (A)

V

OUT

(V)

Output Voltage vs. Output Current,

R

SENSE

= 6mΩ

1.0

0.5

0

1.5

2.0

2.5

3.0

3.5

0 5 10 15 20 25

Output Current (A)

Output Programming, VID4 = 0

1.0

1.5

2.0

2.5

3.0

3.5

1.0

1.5

2.0

2.5

3.0

3.5

1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5

DAC Set Point

V

OUT

(V)V

OUT

(V)

Output Programming, VID4 = 1

DAC Set Point

V

OUT

(V)

18 39 75 150 300 560

C

EXT

(pf)

Oscillator Frequency vs. C

EXT

50

250

450

650

850

1050

1250

Frequency (KHz)