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NM93C66A Rev. E.1
NM93C66A 4K-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature -65°C to +150°C
All Input or Output Voltages +6.5V to -0.3V
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.) +300°C
ESD rating 2000V
Operating Conditions
Ambient Operating Temperature
NM93C66AL/LZ 0°C to +70°C
NM93C66ALE/LZE -40°C to +85°C
NM93C66ALV/LZV -40°C to +125°C
Power Supply (V
CC
) 2.7V to 5.5V
DC and AC Electrical Characteristics V
CC
= 2.7V to 5.5V unless otherwise specified
Symbol Parameter Conditions Min Max Units
I
CCA
Operating Current CS = VIH, SK=1.0 MHz 1 mA
I
CCS
Standby Current CS = V
IL
L 10 µA
LZ (2.7V to 4.5V) 1 µA
I
IL
Input Leakage VIN = 0V to V
CC
±1 µA
I
OL
Output Leakage (Note 2)
I
ILO
Input Leakage ORG Pin ORG tied to V
CC
-1 1 µA
ORG tied to VSS (Note 3) -2.5 2.5
V
IL
Input Low Voltage -0.1 0.15V
CC
V
V
IH
Input High Voltage 0.8V
CC
VCC +1
V
OL
Output Low Voltage IOL = 10µA 0.1V
CC
V
V
OH
Output High Voltage IOH = -10µA 0.9V
CC
f
SK
SK Clock Frequency (Note 4) 0 250 KHz
t
SKH
SK High Time 1 µs
t
SKL
SK Low Time 1 µs
t
SKS
SK Setup Time 0.2 µs
t
CS
Minimum CS Low Time (Note 5) 1 µs
t
CSS
CS Setup Time 0.2 µs
t
DH
DO Hold Time 70 ns
t
DIS
DI Setup Time 0.4 µs
t
CSH
CS Hold Time 0 ns
t
DIH
DI Hold Time 0.4 µs
t
PD
Output Delay 2 µs
t
SV
CS to Status Valid 1 µs
t
DF
CS to DO in Hi-Z CS = V
IL
0.4 µs
t
WP
Write Cycle Time 15 ms
Capacitance TA = 25°C, f = 1 MHz (Note 6)
Symbol Test Typ Max Units
C
OUT
Output Capacitance 5 pF
C
IN
Input Capacitance 5 pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: Typical leakage values are in the 20nA range.
Note 3: ORG pin may draw >1µA when in x8 mode due to the internal pull-up transistor.
Note 4: The shortest allowable SK clock period = 1/f
SK
(as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not
allowable to set 1/fSK = t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to V
IL
) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 6: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range VIL/V
IH
VIL/V
IH
VOL/V
OH
IOL/I
OH
Input Levels Timing Level Timing Level
2.7V ≤ VCC ≤ 5.5V 0.3V/1.8V 1.0V 0.8V/1.5V ±10µA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V 2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)