Fairchild Semiconductor NM93C56VM8X, NM93C56VDWF, NM93C56N, NM93C56MX, NM93C56EN Datasheet

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NM93C56 Rev. E

NM93C56 2048-Bit Serial CMOS EEPROM

(MICROWIRE

TM

Synchronous Bus)

February 2000

© 2000 Fairchild Semiconductor International

NM93C56
2048-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)

General Description

NM93C56 is a 2048-bit CMOS non-volatile EEPROM organized
as 128 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat­ible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the NM93C56 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.

“LZ” and “L” versions of NM93C56 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid­erations.

Functional Diagram

Features

■ Wide VCC 2.7V - 5.5V

■ Typical active current of 200µA

10µA standby current typical
1µA standby current typical (L)

0.1µA standby current typical (LZ)

■ No Erase instruction required before Write instruction

■ Self timed write cycle

■ Device status during programming cycles

■ 40 year data retention

■ Endurance: 1,000,000 data changes

■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

INSTRUCTION

DECODER

CONTROL LOGIC

AND CLOCK

GENERATORS

HIGH VOLTAGE

GENERATOR

AND

PROGRAM

TIMER

INSTRUCTION

REGISTER

ADDRESS

REGISTER

EEPROM ARRAY

READ/WRITE AMPS

DATA IN/OUT REGISTER

16 BITS

DECODER

16

16

DATA OUT BUFFER

CS

SK

DI

DO

V

SS

V

CC

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NM93C56 Rev. E

NM93C56 2048-Bit Serial CMOS EEPROM

(MICROWIRE

TM

Synchronous Bus)

Connection Diagram

Dual-In-Line Package (N)

8–Pin SO (M8) and 8–Pin TSSOP (MT8)

Top View

Package Number

N08E, M08A and MTC08

Pin Names

CS Chip Select

SK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

GND Ground

NC No Connect

V

CC

Power Supply

NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.

Ordering Information

NM 93 C XX LZ E XXX Letter Description

Package N 8-pin DIP

M8 8-pin SO
MT8 8-pin TSSOP

Temp. Range None 0 to 70°C

V -40 to +125°C
E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 5.5V
LZ 2.7V to 5.5V and

<1µA Standby Current

Density 56 2048 bits

C CMOS
CS Data protect and sequential

read

Interface 93 MICROWIRE

Fairchild Memory Prefix

V

CC

NC

GND

CS

SK

DI

DO

1

2

3

4

8

7

6

5

NC

3

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NM93C56 Rev. E

NM93C56 2048-Bit Serial CMOS EEPROM

(MICROWIRE

TM

Synchronous Bus)

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltages +6.5V to -0.3V

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.) +300°C

ESD rating 2000V

Operating Conditions

Ambient Operating Temperature

NM93C56 0°C to +70°C
NM93C56E -40°C to +85°C
NM93C56V -40°C to +125°C

Power Supply (V

CC

) 4.5V to 5.5V

DC and AC Electrical Characteristics V

CC

= 4.5V to 5.5V unless otherwise specified

Symbol Parameter Conditions Min Max Units

I

CCA

Operating Current CS = VIH, SK=1.0 MHz 1 mA

I

CCS

Standby Current CS = V

IL

50 µA

I

IL

Input Leakage VIN = 0V to V

CC

±-1 µA

I

OL

Output Leakage (Note 2)

V

IL

Input Low Voltage -0.1 0.8 V

V

IH

Input High Voltage 2 VCC +1

V

OL1

Output Low Voltage IOL = 2.1 mA 0.4 V

V

OH1

Output High Voltage IOH = -400 µA 2.4

V

OL2

Output Low Voltage IOL = 10 µA 0.2 V

V

OH2

Output High Voltage IOH = -10 µAV

CC

- 0.2

f

SK

SK Clock Frequency (Note 3) 1 MHz

t

SKH

SK High Time 0°C to +70°C 250 ns

-40°C to +125°C 300

t

SKL

SK Low Time 250 ns

t

SKS

SK Setup Time 50 ns

t

CS

Minimum CS Low Time (Note 4) 250 ns

t

CSS

CS Setup Time 100 ns

t

DH

DO Hold Time 70 ns

t

DIS

DI Setup Time 100 ns

t

CSH

CS Hold Time 0 ns

t

DIH

DI Hold Time 20 ns

t

PD

Output Delay 500 ns

t

SV

CS to Status Valid 500 ns

t

DF

CS to DO in Hi-Z CS = V

IL

100 ns

t

WP

Write Cycle Time 10 ms

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www.fairchildsemi.com

NM93C56 Rev. E

NM93C56 2048-Bit Serial CMOS EEPROM

(MICROWIRE

TM

Synchronous Bus)

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltages +6.5V to -0.3V

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.) +300°C

ESD rating 2000V

Operating Conditions

Ambient Operating Temperature

NM93C56L/LZ 0°C to +70°C
NM93C56LE/LZE -40°C to +85°C
NM93C56LV/LZV -40°C to +125°C

Power Supply (V

CC

) 2.7V to 5.5V

DC and AC Electrical Characteristics V

CC

= 2.7V to 5.5V unless otherwise specified

Symbol Parameter Conditions Min Max Units

I

CCA

Operating Current CS = VIH, SK=1.0 MHz 1 mA

I

CCS

Standby Current CS = V

IL

L 10 µA
LZ (2.7V to 4.5V) 1 µA

I

IL

Input Leakage VIN = 0V to V

CC

±1 µA

I

OL

Output Leakage (Note 2)

V

IL

Input Low Voltage -0.1 0.15V

CC

V

V

IH

Input High Voltage 0.8V

CC

VCC +1

V

OL

Output Low Voltage IOL = 10µA 0.1V

CC

V

V

OH

Output High Voltage IOH = -10µA 0.9V

CC

f

SK

SK Clock Frequency (Note 3) 0 250 KHz

t

SKH

SK High Time 1 µs

t

SKL

SK Low Time 1 µs

t

SKS

SK Setup Time 0.2 µs

t

CS

Minimum CS Low Time (Note 4) 1 µs

t

CSS

CS Setup Time 0.2 µs

t

DH

DO Hold Time 70 ns

t

DIS

DI Setup Time 0.4 µs

t

CSH

CS Hold Time 0 ns

t

DIH

DI Hold Time 0.4 µs

t

PD

Output Delay 2 µs

t

SV

CS to Status Valid 1 µs

t

DF

CS to DO in Hi-Z CS = V

IL

0.4 µs

t

WP

Write Cycle Time 15 ms

Capacitance TA = 25°C, f = 1 MHz (Note 5)

Symbol Test Typ Max Units

C

OUT

Output Capacitance 5 pF

C

IN

Input Capacitance 5 pF

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: Typical leakage values are in the 20nA range.

Note 3: The shortest allowable SK clock period = 1/f

SK

(as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t

SKH

and t

SKL

limits must be observed. Therefore, it is not

allowable to set 1/fSK = t

SKHminimum

+ t

SKLminimum

for shorter SK cycle time operation.

Note 4: CS (Chip Select) must be brought low (to V

IL

) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

VCC Range VIL/V

IH

VIL/V

IH

VOL/V

OH

IOL/I

OH

Input Levels Timing Level Timing Level

2.7V ≤ VCC ≤ 5.5V 0.3V/1.8V 1.0V 0.8V/1.5V ±10µA

(Extended Voltage Levels)

4.5V ≤ VCC ≤ 5.5V 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V 2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (CL = 100 pF)