Fairchild Semiconductor NM27C256Q100, NM27C256N200, NM27C256VE150, NM27C256V100, NM27C256QE250 Datasheet
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NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
NM27C256
262,144-Bit (32K x 8) High Performance CMOS EPROM
General Description
The NM27C256 is a 256K Electrically Programmable Read Only
Memory. It is manufactured in Fairchild’s latest CMOS split gate
EPROM technology which enables it to operate at speeds as fast
as 90 ns access time over the full operating range.
The NM27C256 provides microprocessor-based systems extensive storage capacity for large portions of operating system and
application software. Its 90 ns access time provides high speed
operation with high-performance CPUs. The NM27C256 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The NM27C256 is configured in the standard EPROM pinout
which provides an easy upgrade path for systems which are
currently using standard EPROMs.
Block Diagram
July 1998
The NM27C256 is one member of a high density EPROM Family
which range in densities up to 4 Mb.
Features
■ High performance CMOS
—90 ns access time
■ JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
■ Drop-in replacement for 27C256 or 27256
■ Manufacturer’s identification code
DS010833-1
Output Enable
and Chip Enable Logic
Y Decoder
X Decoder
. . . . . . . . .
Output
Buffers
Y Gating
Data Outputs O0 - O
7
V
CC
GND
V
PP
OE
CE/PGM
A0 - A
14
Address
Inputs
© 1998 Fairchild Semiconductor Corporation
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NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Connection Diagrams
Commercial Temp. Range (0°C to +70°C)
VCC = 5V ±10%
Parameter/Order Number Access Time (ns)
NM27C256 Q, N, V 90 90
NM27C256 Q, N, V 100 100
NM27C256 Q, N, V 120 120
NM27C256 Q, N, V 150 150
NM27C256 Q, N, V 200 200
Extended Temp. Range (-40°C to +85°C)
VCC = 5V ±10%
Parameter/Order Number Access Time (ns)
NM27C256 QE, NE, VE 120 120
NM27C256 QE, NE, VE 150 150
NM27C256 QE, NE, VE 200 200
Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.
Package Types: NM27C256 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP
N = Plastic OTP DIP
V = Surface-Mount PLCC
• All Packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower speeds.
Pin Names
Symbol Description
A0–A14 Addresses
CE/PGM Chip Enable/Program
OE Output Enable
O0–O7 Outputs
XX Don’t Care (during Read)
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
A
19
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C080 27C040 27C040
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
DlP
NM27C256
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C512 27C512
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C010
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C020 27C02027C010
V
CC
XX/PGM
A
17
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
27C080
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
CC
XX/PGM
XX
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
V
CC
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins.
A
8
A
9
A
11
XX
OE
A
10
CE/PGM
O
7
O
6
A
6
A
5
A
4
A
3
A
2
A
1
A
0
XX
O
0
A7A12VPPXX
VCCA14A
13
O1O
2
GND
XX
O
3O4O5
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
4 3 2 1 32 31 30
DS010833-2
DS010833-3
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NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Storage Temperature -65°C to +150°C
All Input Voltages except A9 with
Respect to Ground -0.6V to +7V
VPP and A9 with Respect
to Ground -0.7V to +14V
VCC Supply Voltage with
Respect to Ground -0.6V to +7V
ESD Protection > 2000V
All Output Voltages with
Respect to Ground VCC + 1.0V to GND -0.6V
Operating Range
Range Temperature V
CC
Comm’l 0°C to +70°C +5V ±10%
Industrial -40°C to +85°C +5V ±10%
Read Operation
DC Electrical Characteristics Over Operating Range with V
PP
= V
CC
Symbol Parameter Test Conditions Min Max Units
V
IL
Input Low Level -0.5 0.8 V
V
IH
Input High Level 2.0 VCC +1 V
V
OL
Output Low Voltage IOL = 2.1 mA 0.4 V
V
OH
Output High Voltage IOH = -2.5 mA 3.5 V
I
SB1
VCC Standby Current CE = VCC ±0.3V 100 µA
(Note 11) (CMOS)
I
SB2
VCC Standby Current (TTL) CE = V
IH
1mA
I
CC1
VCC Active Current CE = OE = VIL,f=5 MHz 35 mA
TTL Inputs Inputs = VIH or VIL, I/O = 0 mA
I
PP
VPP Supply Current VPP = V
CC
10 µA
V
PP
VPP Read Voltage VCC - 0.7 V
CC
V
I
LI
Input Load Current VIN = 5.5V or GND -1 1 µA
I
LO
Output Leakage Current V
OUT
= 5.5V or GND -10 10 µA
AC Electrical Characteristics Over Operating Range with V
PP
= V
CC
Symbol Parameter 90 100 120 150 200 Units
Min Max Min Max Min Max Min Max Min Max
t
ACC
Address to Output Delay
90 100 120 150 200 ns
t
CE
CE to Output Delay 90 100 120 150 200
t
OE
OE to Output Delay 35 50 50 50 50
t
DF
Output Disable to 30 30 35 45 45
(Note 2) Output Float
t
OH
Output Hold from 00000
(Note 2) Addresses,
CE or OE, Whichever
Occurred First
Capacitance (Note 2) T
A
= +25˚C, f = 1 MHz
Symbol Parameter Conditions Typ Max Units
C
IN
Input Capacitance VIN = 0V 6 12 pF
C
OUT
Output Capacitance V
OUT
= 0V 9 12 pF
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NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times ≤ 5 ns
Input Pulse Levels 0.45 to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs 0.8V and 2.0V
Outputs 0.8V and 2.0V
AC Waveforms (Note 6) (Note 7) (Note 9)
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
- tOE after the falling edge of CE without impacting t
ACC
.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL = 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10:Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11:CMOS inputs: VIL = GND ±0.3V, VIH = VCC ±0.3V.
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
Symbol Parameter Conditions Min Typ Max Units
ADDRESSES VALID
VALID OUTPUT
Hi-ZHi-Z
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
ADDRESSES
CE
OE
OUTPUT
t
OE
(Note 3)
t
ACC
(Note 3)
t
CE
t
CE
(Notes 4, 5)
t
OH
t
DF
(Notes 4, 5)
DS010833-4
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