Fairchild Semiconductor NM25C020LEM8X, NM25C020LEMT8, NM25C020LEMT8X, NM25C020LZM8, NM25C020LZM8X Datasheet

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NM25C020 Rev. D.1

NM25C020 2K-Bit Serial CMOS EEPROM

(Serial Periphrial Interface (SPI) Synchronous Bus)

March 1999

© 1999 Fairchild Semiconductor Corporation

NM25C020
2K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)

General Description

The NM25C020 is a 2048-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C020 is designed for data
storage in applications requiring both non-volatile memory and in­system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C020 is imple­mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.

The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.

BLOCK WRITE protection is provided by programming the STA­TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc­tions are provided for data protection.

Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.

Block Diagram

Features

■ 2.1 MHz clock rate @ 2.7V to 5.5V

■ 2048 bits organized as 256 x 8

■ Multiple chips on the same 3-wire bus with separate chip

select lines

■ Self-timed programming cycle

■ Simultaneous programming of 1 to 4 bytes at a time

■ Status register can be polled during programming to monitor

READY/BUSY

■ Write Protect (WP) pin and write disable instruction for both
hardware and software write protection

■ Block write protect feature to protect against accidental
writes

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP

DS012400-1

Instruction

Decoder

Control Logic

and Clock

Generators

High Voltage

Generator

and

Program

Timer

Instruction

Register

Program
Enable

Data In/Out Register

8 Bits

Data Out

Buffer

Non-Volatile

Status Register

Decoder
1 of 256

Address
Counter/
Register

EEPROM Array

2048 Bits
(256 x 8)

Read/Write Amps

CS

HOLD

SCK

V

CC

V

SS

V

PP

WP

SI

SO

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NM25C020 Rev. D.1

NM25C020 2K-Bit Serial CMOS EEPROM

(Serial Periphrial Interface (SPI) Synchronous Bus)

Connection Diagram

Dual-In-Line Package (N), SO Package (M8),

and TSSOP Package (MT8)

Top View

See Package Number N08E (N), M08A (M8), and MTC08 (MT8)

Pin Names

CS Chip Select Input

SO Serial Data Output
WP Write Protect
V

SS

Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD Suspends Serial Data

V

CC

Power Supply

Ordering Information
NM 25 C XX LZ E XX Letter Description

Package N 8-pin DIP

M8 8-pin SO
MT8 8-pin TSSOP

Temp. Range None 0 to 70°C

V -40 to +125°C
E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 4.5V
LZ 2.7V to 4.5V and

<1µA Standby Current

Density/Mode 020 2K, mode 0

C CMOS technology

Interface 25 SPI

NM Fairchild Nonvolatile

Memory Prefix

CS

SO

WP
V

SS

V

CC

HOLD
SCK
SI

8
7
6
5

1
2
3
4

NM25C020

DS012400-2

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NM25C020 Rev. D.1

NM25C020 2K-Bit Serial CMOS EEPROM

(Serial Periphrial Interface (SPI) Synchronous Bus)

Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C
All Input or Output Voltage with

Respect to Ground +6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.) +300°C
ESD Rating 2000V

Operating Conditions

Ambient Operating Temperature

NM25C020 0°C to +70°C
NM25C020E -40°C to +85°C
NM25C020V -40°C to +125°C

Power Supply (VCC) 4.5V to 5.5V

DC and AC Electrical Characteristics 4.5V ≤ V

CC

≤ 5.5V (unless otherwise specified)

Symbol Parameter Conditions Min Max Units

I

CC

Operating Current CS = V

IL

3mA

I

CCSB

Standby Current CS = V

CC

50 µA

I

IL

Input Leakage VIN = 0 to V

CC

-1 +1 µA

I

OL

Output Leakage V

OUT

= GND to V

CC

-1 +1 µA

V

IL

CMOS Input Low Voltage -0.3 VCC * 0.3 V

V

IH

CMOS Input High Voltage 0.7 * VCCVCC + 0.3 V

V

OL

Output Low Voltage IOL = 1.6 mA 0.4 V

V

OH

Output High Voltage IOH = -0.8 mA VCC - 0.8 V

f

OP

SCK Frequency 2.1 MHz

t

RI

Input Rise Time 2.0 µs

t

FI

Input Fall Time 2.0 µs

t

CLH

Clock High Time (Note 2) 190 ns

t

CLL

Clock Low Time (Note 2) 190 ns

t

CSH

Min CS High Time (Note 3) 240 ns

t

CSS

CS Setup Time 240 ns

t

DIS

Data Setup Time 100 ns

t

HDS

HOLD Setup Time 90 ns

t

CSN

CS Hold Time 240 ns

t

DIN

Data Hold Time 100 ns

t

HDN

HOLD Hold Time 90 ns

t

PD

Output Delay CL = 200 pF 240 ns

t

DH

Output Hold Time 0 ns

t

LZ

HOLD to Output Low Z 100 ns

t

DF

Output Disable Time CL = 200 pF 240 ns

t

HZ

HOLD to Output High Z 100 ns

t

WP

Write Cycle Time 1–4 Bytes 10 ms

Capacitance T

A

= 25°C, f = 2.1/1 MHz (Note 4)

Symbol Test Typ Max Units

C

OUT

Output Capacitance 3 8 pF

C

IN

Input Capacitance 2 6 pF

AC Test Conditions

Output Load CL = 200 pF
Input Pulse Levels 0.1 * VCC – 0.9 * V

CC

Timing Measurement Reference Level 0.3 * VCC - .07 * V

CC

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, t

CLH

+ t

CLL

must be equal to or greater than 1/fOP. For

example, if the 2.1MHz period = 476ns and t

CLH

= 190ns, t

CLL

must be 286ns.

Note 3: CS must be brought high for a minimum of t

CSH

between consecutive instruction cycles.

Note 4: This parameter is periodically sampled and not 100% tested.