Fairchild Semiconductor NDT453N Datasheet
NDT453N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
September 1996
Power SOT N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
8A, 30V. R
R
High density cell design for extremely low R
= 0.028Ω @ VGS = 10V.
DS(ON)
= 0.042Ω @ VGS = 4.5V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
voltage applications such as notebook computer power
management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
___________________________________________________________________________________________
D
G
D S
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise not
A
Symbol Parameter NDT453N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) ±8 A
- Pulsed ±15
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT453N Rev. D1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
I
DSS
I
GSSF
I
GSSR
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 15 V, V
Output Capacitance 560 pF
Reverse Transfer Capacitance 190 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time
Turn - On Rise Time 20 35 ns
Turn - Off Delay Time 40 50 ns
Turn - Off Fall Time 35 50 ns
Total Gate Charge
Gate-Source Charge 4.5 nC
Gate-Drain Charge 9.5 nC
VDS = 24 V, V
GS
= 0 V
TJ= 55°C
VGS = 20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
TJ= 125°C 0.7 1.5 2.2
VGS = 10 V, ID = 8.0 A
TJ= 125°C 0.03 0.045
VGS = 4.5 V, ID = 6.7 A
TJ= 125°C 0.047 0.075
VGS = 10 V, VDS = 5 V
15 A
VGS = 4.5 V, VDS = 5 V 10
VDS = 15 V, ID = 8.0 A
= 0 V,
f = 1.0 MHz
GS
VDD = 25 V, ID = 1 A,
V
= 10 V, R
GEN
GEN
= 6 Ω
VDS = 15 V, ID = 8.0 A, VGS = 10 V
1 µA
10 µA
100 nA
1 2 3 V
0.022 0.028
0.035 0.042
14 S
890 pF
10 15 ns
28 35 nC
Ω
NDT453N Rev. D1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
t
rr
Notes:
1. R
SD
JA
θ
design while R
P
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.3 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
T
(t)
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θ
J C
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
+R
2
= I
(t) × R
DS(ON ) T
D
(t)
θ
CA
J
1a
VGS = 0 V, IS = 8.0 A
(Note 2)
VGS = 0 V, IS = 2 A, dIF/dt = 100A/µs
1b
1c
0.8 1.3 V
100 ns
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT453N Rev. D1
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