Fairchild Semiconductor NDT451N Datasheet
NDT451N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
September 1996
Power SOT N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
5.5A, 30V. R
High density cell design for extremely low R
= 0.05Ω @ VGS = 10V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
performance. These devices are particularly suited for low
voltage applications such as DC motor control and
DC/DC conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
___________________________________________________________________________________________________________
Absolute Maximum Ratings T
D
G
D S
= 25°C unless otherwise noted
A
D
G
S
Symbol Parameter NDT451N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) ±5.5 A
- Pulsed ±25
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
© 1997 Fairchild Semiconductor Corporation
NDT451N Rev. C2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
I
I
DSS
DSS
GSSF
GSSR
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ = 55°C
2 µA
20 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 3 V
TJ = 125°C 0.7 1.2 2.2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 5.5 A
TJ = 125°C
0.042 0.05
0.065 0.1
Ω
VGS = 4.5 V, ID = 4.3 A 0.064 0.08
I
D(on)
On-State Drain Current
VGS = 10 V, VDS = 5 V
18 A
VGS = 4.5 V, VDS = 5 V 15
g
FS
Forward Transconductance
VDS = 10 V, ID = 5.5 A
6 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, VGS = 0 V,
Output Capacitance 370 pF
f = 1.0 MHz
730 pF
Reverse Transfer Capacitance 140 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 15 25 ns
VDD = 15 V, ID = 1.0 A,
V
= 10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 19 40 ns
Turn - Off Fall Time 10 30 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.8 3 nC
Gate-Drain Charge 4.5 7 nC
VDS = 10 V,
ID = 5.5 A, VGS = 10 V
20 30 ns
16 25 nC
NDT451N Rev. C2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
θ
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper
Maximum Continuous Drain-Source Diode Forward Current 2.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
2
= I
(t) × R
DS(O N ) T
D
(t)
J
1a
VGS = 0 V, IS = 5.5 A
1b
(Note 2)
1c
0.8 1.2 V
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT451N Rev. C2
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