Fairchild Semiconductor NDT451AN Datasheet
NDT451AN
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
July 1996
Power SOT N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as DC motor control and DC/DC
7.2A, 30V. R
R
High density cell design for extremely low R
= 0.035Ω @ VGS = 10V
DS(ON)
= 0.05Ω @ VGS = 4.5V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
conversion where fast switching, low in-line power loss,
and resistance to transients are needed.
________________________________________________________________________________
D
G
D S
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDT451AN Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) ± 7.2 A
- Pulsed ± 25
P
D
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c) 1.1
TJ,T
Operating and Storage Temperature Range -65 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT451AN Rev. D
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
1 µA
TJ = 55°C
10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 3 V
TJ = 125°C 0.7 1.2 2.2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 7.2 A
TJ = 125°C
0.03 0.035
0.042 0.063
Ω
VGS = 4.5 V, ID = 6.0 A 0.042 0.05
0.058 0.09
25 A
15
11 S
I
g
D(on)
FS
On-State Drain Current
Forward Transconductance
TJ = 125°C
VGS = 10 V, VDS = 5 V
VGS = 4.5 V, VDS = 5 V
VDS = 10 V, ID = 7.2 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 370 pF
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 250 pF
720 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
V
= 10 V, R
Turn - On Rise Time 13 30 ns
GEN
GEN
= 6 Ω
12 20 ns
Turn - Off Delay Time 29 50 ns
Turn - Off Fall Time 10 20 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 2.3 nC
ID = 7.2 A, VGS = 10 V
19 30 nC
Gate-Drain Charge 5.5 nC
NDT451AN Rev. D
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.3 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 7.2A
(Note 2)
0.9 1.3 V
Reverse Recovery Time VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
1a
T
J−TA
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
=
(t)
R
θJ C+RθCA
2
= I
(t) × R
DS(ON)T
D
(t)
J
1b 1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT451AN Rev. D
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