Fairchild Semiconductor NDT410EL Datasheet
NDT410EL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
August 1996
Power SOT N-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance, provide superior
2.1A 100V. R
High density cell design for extremely low R
= 0.25Ω @ VGS = 5V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
switching performance, and withstand high energy pulses
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
___________________________________________________________________________________________
D
G
D S
D
G
S
ABSOLUTE MAXIMUM RATINGS T
= 25°C unless otherwise noted
A
Symbol Parameter NDT410EL Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 100 V
Gate-Source Voltage 20 V
Drain Current - Continuous (Note 1a) 2.1 A
- Pulsed 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT410EL Rev. B1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE AVALANCHE RATINGS (Note 2)
W
DSS
I
AR
Single Pulse Drain-Source Avalanche Energy VDD = 50 V, ID = 10A 15 mJ
Maximum Drain-Source Avalanche Current 10 A
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
VGS = 0 V, ID = 250 µA
VDS = 80 V, V
GS
= 0 V
TJ= 55°C
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
100 V
1 µA
10 µA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 2 V
TJ= 125°C
0.65 1.1 1.5
Static Drain-Source On-Resistance VGS = 5 V, ID = 2.1 A 0.2 0.25
TJ= 125°C
0.37 0.5
On-State Drain Current VGS = 5 V, VDS = 5 V 10 A
Forward Transconductance
VDS = 10 V, ID = 2.1 A
6 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 25 V, V
Output Capacitance 85 pF
f = 1.0 MHz
GS
= 0 V,
528 pF
Reverse Transfer Capacitance 20 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 72 120 ns
VDD = 50 V, ID = 2.1 A,
V
= 5 V, R
GEN
GEN
= 25 Ω
Turn - Off Delay Time 49 80 ns
Turn - Off Fall Time 47 80 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.5 nC
Gate-Drain Charge 5.6 nC
VDS = 80 V, ID = 2.1 A, VGS = 5 V
9 20 ns
16 nC
10
NDT410EL Rev. B1
ELECTRICAL CHARACTERISTICS (T
TJ−
T
θJA
TJ−
T
θJC+RθCA
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 2.3 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
A
=
(t)
R
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.006 in2 pad of 2oz copper.
A
2
=
R
(t)
= I
× R
DS(ON)@T
D
(t)
J
1a
VGS = 0 V, IS = 2.3 A
(Note 2)
VGS = 0 V, IS = 2.3 A, dIF/dt = 100A/µs
1b
1c
1.3 V
150 ns
is guaranteed by
JC
θ
NDT410EL Rev. B1
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