Fairchild Semiconductor NDT014L Datasheet
August 1996
NDT014L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology.This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation
modes.Thesedevices are particularly suited for low voltage
applications such as DC motor control and DC/DC
conversion where fast switching, low in-line power loss, and
resistance to transients are needed.
_________________________________________________________________________________
2.8 A, 60 V. R
R
High density cell design for extremely low R
= 0.2 Ω @ VGS = 4.5 V
DS(ON)
= 0.16 Ω @ VGS = 10 V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
D
G
S
Absolute Maximum Ratings T
D
G
A
D S
= 25°C unless otherwise noted
Symbol Parameter NDT014L Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 60 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) ± 2.8 A
- Pulsed ± 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
© 1997 Fairchild Semiconductor Corporation
NDT014L Rev.D
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
Zero Gate Voltage Drain Current
VDS = 60 V, V
GS
= 0 V
TJ = 55°C
25 µA
250 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 3 V
0.8 1.1 2
0.17 0.2
Static Drain-Source On-Resistance
TJ = 125°C
VGS= 4.5 V, ID = 2.8 A
Ω
TJ = 125°C 0.22 0.36
0.12 0.16
10
I
G
D(on)
VGS = 10 V, ID = 3.4 A
On-State Drain Current VGS = 4.5 V , VDS = 5 V 5 A
VGS = 10 V, VDS = 5 V
FS
Forward Transconductance VGS = 5 V, ID = 2.8 A 4.2 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 70 pF
VDS = 30 V, V
f = 1.0 MHz
= 0 V,
GS
Reverse Transfer Capacitance 27 pF
214 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 14 25 ns
VDD = 30 V, ID = 3 A,
V
= 10 V, R
GEN
GEN
= 12 Ω
Turn - Off Delay Time 15 28 ns
Turn - Off Fall Time 10 18 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.8 nC
Gate-Drain Charge 1.4 nC
VDS = 10 V,
ID = 2.8 A, VGS = 4.5 V
6 12 ns
3.6 5 nC
NDT014L Rev.D
Electrical Characteristics (T
TJ−
T
θJA
TJ−
T
θJC+RθCA
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
D
solder mounting surface of the drain pins. R
R
Maximum Continuous Drain-Source Diode Forward Current 2.3 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 2.3 A (Note 2)
0.85 1.3 V
Reverse Recovery Time VGS = 0 V, IF = 2.3 A dIF/dt = 100 A/µs 140 ns
A
(t)
=
(t)
R
is found to be:
JA
θ
a. 42oC/W with 1 in2 of 2 oz copper mounting pad.
b. 95oC/W with 0.066 in2 of 2 oz copper mounting pad.
c. 110oC/W with 0.0123 in2 of 2 oz copper mounting pad.
A
2
=
R
(t)
= I
× R
DS(ON)@T
D
(t)
is guaranteed by design while R
JC
θ
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as theP
JA
θ
J
is defined by users. For general reference: Applications on 4.5"x5" FR-4 PCB under still air environment, typical
CA
θ
1a
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
1b
1c
NDT014L Rev.D
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