Fairchild Semiconductor NDS9959 Datasheet
NDS9959
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
February 1996
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as DC motor control and DC/DC conversion where fast
2.0A, 50V. R
High density cell design for extremely low R
= 0.3Ω @ V
DS(ON)
= 10V
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
switching, low in-line power loss, and resistance to transients
are needed.
_________________________________________________________________________________
5
6
7
8
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS9959 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 50 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous @ TA = 25°C (Note 1a) ± 2.0 A
- Continuous @ TA = 70°C (Note 1a)
± 1.6
- Pulsed @ TA = 25°C ± 8
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
4
3
2
1
© 1997 Fairchild Semiconductor Corporation
NDS9959.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 50 V
Zero Gate Voltage Drain Current
VDS = 40 V, V
GS
= 0 V
TJ= 55°C
2 µA
25 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 2 3 4 V
Static Drain-Source On-Resistance
VGS = 10 V, ID = 1.5 A
VGS = 5 V, ID = 0.6 A
0.3
0.5
On-State Drain Current VGS = 10 V, VDS = 5 V 8 A
Forward Transconductance
VDS = 15 V, ID = 2.0 A
1 2.7 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 50 85 pF
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 12 25 pF
152 250 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 30 V, ID = 0.6 A,
Turn - On Rise Time 8 70 ns
Turn - Off Delay Time 9 100 ns
VGS = 10 V, R
R
= 6 Ω
GEN
= 50 Ω,
L
4 40 ns
Turn - Off Fall Time 11 70 ns
Total Gate Charge VDS = 25 V,
Gate-Source Charge 1.1 nC
ID = 1.3 A, VGS = 10 V
4.3 15 nC
Gate-Drain Charge 1.5 nC
NDS9959.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
P
design while R
Typical R
Maximum Continuos Drain-Source Diode Forward Current 1.8 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.25 A
(Note 2)
0.84 1.2 V
Reverse Recovery Time VGS = 0V, IF = 1.25 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
1a
J−TA
2
= I
(t) × R
DS(ON)T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9959.SAM
Loading...