Fairchild Semiconductor NDS9957 Datasheet
February 1996
NDS9957
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to transients
are needed.
_______________________________________________________________________________
2.6A, 60V. R
High density cell design for extremely low R
= 0.16Ω @ V
DS(ON)
= 10V.
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
Symbol Parameter NDS9957 Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
θ
R
θ
Drain-Source Voltage 60 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) ± 2.6 A
- Pulsed ± 10
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
= 25°C unless otherwise noted
A
© 1997 Fairchild Semiconductor Corporation
NDS9957.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
Zero Gate Voltage Drain Current
VDS = 48 V, V
GS
= 0 V
1 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1 1.5 3 V
TA = 125°C 0.7 1.1 2.2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 2.6 A
TA = 125°C
VGS = 4.5 V, ID = 2.1 A
0.145 0.16
0.25 0.3
0.19 0.25
Ω
TA = 125°C 0.32 0.5
I
g
D(on)
FS
On-State Drain Current
VGS = 10 V, VDS = 5 V
Forward Transconductance VDS = 5 V, ID = 2.6 A 4 S
10 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 60 pF
VDS = 30 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 20 pF
200 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 30 V, ID = 1 A,
Turn - On Rise Time 11 25 ns
VGS = 10 V,R
GEN
= 6 Ω
6 20 ns
Turn - Off Delay Time 17 30 ns
Turn - Off Fall Time 4 15 ns
Total Gate Charge VDS = 30 V,
Gate-Source Charge 2.8 nC
ID = 2.6 A, VGS = 10 V
7.5 12 nC
Gate-Drain Charge 0.8 nC
NDS9957.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper
Maximum Continuos Drain-Source Diode Forward Current 1.7 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
J−TA
2
= I
(t) × R
DS(ON ) T
D
(t)
J
1a
VGS = 0 V, IS = 2.6 A
1b
(Note 2)
1c
0.9 1.2 V
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9957.SAM
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