February 1996
NDS9956A
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as DC/DC conversion and DC motor
control where fast switching, low in-line power loss, and
resistance to transients are needed.
________________________________________________________________________________
3.7A, 30V. R
High density cell design for extremely low R
= 0.08Ω @ V
DS(ON)
= 10V
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
5
6
7
8
Symbol Parameter NDS9956A Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) ± 3.7 A
- Pulsed ± 15
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
© 1997 Fairchild Semiconductor Corporation
NDS9956A.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
2 µA
TJ = 55°C
25 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.7 2.8 V
TJ = 125°C 0.7 1.2 2.2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 2.2 A
TJ = 125°C
0.06 0.08
0.08 0.13
Ω
VGS = 4.5 V, ID = 1.0 A 0.08 0.11
0.11 0.18
15 A
3.5
6 S
I
g
D(on)
TJ = 125°C
On-State Drain Current
VGS = 10 V, VDS = 10 V
VGS = 4.5 V, VDS = 10 V
FS
Forward Transconductance
VDS = 15 V, ID = 3.7 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 225 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 85 pF
320 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
V
= 10 V, R
Turn - On Rise Time 13 20 ns
GEN
GEN
= 6 Ω
10 20 ns
Turn - Off Delay Time 21 50 ns
Turn - Off Fall Time 5 50 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 1.5 nC
ID = 3.7 A, VGS = 10 V
9.5 27 nC
Gate-Drain Charge 3.3 nC
NDS9956A.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current 1.2 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.25 A
(Note 2)
0.8 1.3 V
Reverse Recovery Time VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
1a
J−TA
2
= I
(t) × R
DS (ON ) T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9956A.SAM