Fairchild Semiconductor NDS9948 Datasheet
NDS9948
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
February 1996
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process has
been especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as notebook computer power management and other battery
-2.3A, -60V. R
High density cell design for low R
= 0.25Ω @ V
DS(ON)
= -10V.
GS
DS(ON)
.
High power and current handling capability in a widely
used surface mount package.
Dual MOSFET in surface mount package.
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
______________________________________________________________________________
5
6
7
8
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS9948 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -60 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous TA = 25°C (Note 1a)
- Pulsed TA = 25°C
± 2.3 A
± 10
- Continuous TA = 70°C (Note 1a) ± 1.8
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
4
3
2
1
© 1997 Fairchild Semiconductor Corporation
NDS9948.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -60 V
Zero Gate Voltage Drain Current
VDS = -40 V, V
GS
= 0 V
T
J
= 55°C
-2 µA
-25 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -2.4 -3 V
TJ =125°C -0.8 -2 -2.6
R
DS(ON)
Static Drain-Source On-Resistance
VGS = -10 V, ID = -2.3 A
TJ =125°C
0.21 0.25
0.3 0.4
Ω
VGS = -4.5 V, ID = -1.6 A 0.36 0.5
I
D(on)
g
FS
On-State Drain Current
VGS = -10 V, VDS = -5 V
Forward Transconductance VDS = -15 V, ID = -2.3 A 3.5 S
-10 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 140 pF
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 40 pF
570 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -30 V, ID = -1 A,
V
= -10 V, R
Turn - On Rise Time 20 40 ns
GEN
GEN
= 6 Ω
8 15 ns
Turn - Off Delay Time 20 40 ns
Turn - Off Fall Time 5 20 ns
Total Gate Charge VDS = -30 V,
Gate-Source Charge 2 5 nC
ID = -2.3 A, VGS = -10 V
16 25 nC
Gate-Drain Charge 4 8 nC
NDS9948.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper
Maximum Continuous Drain-Source Diode Forward Current -1.7 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
T
J−TA
θJ A
JA
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpperr.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
J−TA
=
(t)
R
θ
J C
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
2
= I
(t) × R
DS(ON ) T
D
+R
(t)
θ
CA
J
1a
VGS = 0 V, IS = -2.3 A
1b
(Note 2)
1c
-0.98 -1.2 V
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9948.SAM
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