Fairchild Semiconductor NDS9936 Datasheet
NDS9936
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
February 1996
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as DC/DC conversion,
disk drive motor control, and other battery powered circuits
where fast switching, low in-line power loss, and resistance to
5A, 30V. R
High density cell design for extremely low R
= 0.05Ω @ V
DS(ON)
= 10V.
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
transients are needed.
________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS9936 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous @ TA = 25°C (Note 1a)
- Continuous @ TA = 70°C (Note 1a)
± 5.0 A
± 4.0
- Pulsed @ TA = 25°C ± 40
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
NDS9936.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ= 55°C
2 µA
20 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.4 3 V
TJ=125°C 0.7 1.1 2.2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 5 A
TJ=125°C
0.044 0.05
0.066 0.1
Ω
VGS = 4.5 V, ID = 3.9 A 0.066 0.08
TJ=125°C 0.099 0.16
I
D(on)
On-State Drain Current
VGS = 10 V, VDS = 10 V
40 A
VGS = 4.5 V, VDS = 10 V 20
g
FS
Forward Transconductance
VDS = 10 V, ID = 3.5 A
3 8 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 15 V, VGS = 0 V,
Output Capacitance 315 pF
f = 1.0 MHz
525 pF
Reverse Transfer Capacitance 185 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(ON)
t
r
t
D(OFF)
t
f
Q
Q
Q
Turn - On Delay Time
Turn - On Rise Time 10 25 ns
VDD = 15 V, ID = 1 A,
VGS = 10 V, R
GEN
= 6 Ω
Turn - Off Delay Time 25 50 ns
Turn - Off Fall Time 10 50 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.5 nC
Gate-Drain Charge 3.7 nC
VDS = 15 V,
ID = 5 A, VGS = 10 V
12 30 ns
17 35 nC
© 1993 Fairchild Semiconductor Corporation
NDS9936.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Maximum Continuos Drain-Source Diode Forward Current 1.7 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.7 A
(Note 2)
0.78 1.2 V
Reverse Recovery Time VGS = 0V, IF = 5 A, dIF/dt = 100 A/µs 70 160 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
1a
J−TA
2
= I
(t) × R
DS(ON)T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9936.SAM
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