Fairchild Semiconductor NDS9410S Datasheet
NDS9410S
Single N-Channel Enhancement Mode Field Effect Transistor
General Description Features
February 1997
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
7.0 A, 30 V. R
High density cell design for extremely low R
= 0.03 Ω @ V
DS(ON)
= 10 V.
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
ABSOLUTE MAXIMUM RATINGS T
= 25°C unless otherwise noted
A
Symbol Parameter NDS9410S Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 7 A
- Pulsed 25
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1.2
1
THERMAL CHARACTERISTICS
R
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
JC
NDS9410S Rev.B
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
I
I
DSS
DSS
GSSF
GSSR
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ= 55°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 2 2.2 4 V
TJ= 125°C
1.4 1.6 2.8
Static Drain-Source On-Resistance VGS = 10 V, ID = 7 A 0.026 0.03
TJ= 125°C
0.036 0.055
On-State Drain Current VGS = 10 V, VDS = 5 V 25
Forward Transconductance
VDS = 10 V, ID = 7 A
11 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 15 V, V
Output Capacitance 490 pF
f = 1.0 MHz
GS
= 0 V,
670 pF
Reverse Transfer Capacitance 150 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
Turn - On Delay Time
Turn - On Rise Time 15 30 ns
VDD = 10 V, ID = 1 A,
V
= 10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 19 40 ns
Turn - Off Fall Time 12 25 ns
Total Gate Charge
Gate-Source Charge 4 nC
VDS = 10 V,
ID = 7 A, VGS = 10 V
Gate-Drain Charge 6 nC
10 20 ns
18 25 nC
NDS9410S Rev.B
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
Typical R
design while R
P
Maximum Continuous Drain-Source Diode Forward Current 2.1 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.
J−TA
θJ A
T
J−TA
=
(t)
R
+R
θ
J C
2
= I
(t) × R
D
DS(O N ) T
(t)
θ
CA
J
1a
VGS = 0 V, IS = 2.1A
1b
(Note 2)
1c
1.2 V
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
NDS9410S Rev.B
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