Fairchild Semiconductor NDS9407 Datasheet
NDS9407
Single P-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1999
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications
such as notebook computer power management and other
battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
-3.0A, -60V. R
R
High density cell design for extremely low R
High power and current handling capability in a widely used
surface mount package.
= 0.15Ω @ V
DS(ON)
DS(ON)
= 0.24Ω @ V
=-10V
GS
=-4.5V.
GS
.
DS(ON)
_______________________________________________________________________________________
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
5
6
7
8
4
3
2
1
Symbol Parameter NDS9407 Units
V
DSS
V
GSS
I
D
P
D
TJ,T
Drain-Source Voltage -60 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous TA = 25°C (Note 1a)
- Continuous TA = 70°C
- Pulsed TA = 25°C
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
± 3.0 A
± 2.4
± 12
1.2
1
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
JC
©1999 Fairchild Semiconductor Corporation
NDS9407.SAM Rev. B
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VGS = 0 V, ID = -250 µA
VDS = -48 V, V
GS
= 0 V
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
TA= 55°C
-60 V
-1 µA
-10 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
D(on)
g
GS (th)
FS
DS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VDS = VGS, ID = -250 µA
TA = 125°C
VGS = -10 V, ID = -3.0 A
TA = 125°C
VGS = -4.5 V, ID = -1.6 A
TA = 125°C
VGS = -10 V, VDS = -5 V
VDS = -15 V, ID = -3.0 A
-1 -2.3 V
-0.8 -1.8
0.08 0.15
0.13 0.3
0.135 0.24
0.2 0.48
-12 A
6.8 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 290 pF
VDS = -30 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 80 pF
1400 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
t
r
t
D(off)
t
f
Q
Q
Q
Turn - On Delay Time
Turn - On Rise Time 12 40 ns
VDD = -25 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 55 100 ns
Turn - Off Fall Time 22 45 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 4 nC
Gate-Drain Charge 10 nC
VDS = -30 V,
ID = -3.0 A, VGS = -10 V
12 30 ns
37 50 nC
NDS9407.SAM Rev. B
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
Scale 1 : 1 on letter size paper
Maximum Continuous Drain-Source Diode Forward Current -2.1 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θJA
guaranteed by design while R
TJ−T
P
D
Typical R
A
(t) =
=
R
(t)
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
θJA
a. 50oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz cpper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz cpper.
is determined by the user's board design.
θCA
TJ−T
R
θJ C+RθCA
2
A
= I
(t)× R
DS(ON)@T
D
(t)
J
1a 1b
VGS = 0 V, IS = -2.5 A
(Note 2)
1c
-0.9 -1.2 V
is
θJC
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9407.SAM Rev. B
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