Fairchild Semiconductor NDS8961 Datasheet
NDS8961
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1997
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance.These devices are particularly
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power
3.1 A, 30 V. R
R
High density cell design for extremely low R
= 0.1 Ω @ V
DS(ON)
= 0.15 Ω @ V
DS(ON)
= 10 V
GS
= 4.5 V.
GS
.
DS(ON)
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
loss, and resistance to transients are needed.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
Symbol Parameter
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 3.1 A
- Pulsed 10
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
= 25°C unless otherwise noted
A
NDS8961
NDS8961 Rev.D
Units
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
1 µA
TJ = 55oC 10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1 1.6 3 V
TJ = 125oC 0.7 1.2 2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 3.1 A
0.072 0.1
Ω
TJ = 125oC 0.107 0.18
0.116 0.15
4
I
g
D(on)
VGS = 4.5 V, ID = 2.6 A
On-State Drain Current VGS = 10 V, VDS = 5 V 10 A
VGS = 4.5 V, VDS = 5 V
FS
Forward Transconductance VDS = 10 V, ID = 3.1 A 4.3 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 120 pF
VDS= 15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 40 pF
190 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 15 30 ns
VGS = 10 V, R
GEN
= 6 Ω
7 15 ns
Turn - Off Delay Time 14 28 ns
Turn - Off Fall Time 3 6 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 1.2 nC
ID = 3.1 A, VGS = 10 V
7.1 10 nC
Gate-Drain Charge 1.9 nC
NDS8961 Rev.D
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
−
T
J
=
R
θJA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
−
T
T
T
A
J
A
=
(t)
R
θJC+RθCA
2
= I
(t) ×R
DS(ON ) T
D
(t)
J
1a
VGS = 0 V, IS = 1.3 A (Note 2)
1b
1c
0.79 1.2 V
is guaranteed by
JC
θ
NDS8961 Rev.D
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