Fairchild Semiconductor NDS8958 Datasheet

NDS8958
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
N-Channel 5.3A, 30V, R P-Channel -4.0A, -30V, R
High density cell design or extremely low R
=0.035 @ V
DS(ON)
=0.065@ V
DS(ON)
GS
GS
DS(ON)
=10V.
=-10V.
.
High power and current handling capability in a widely used surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter N-Channel P-Channel Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 -30 V
Gate-Source Voltage 20 -20 V
Drain Current - Continuous (Note 1a) 5.3 -4 A
- Pulsed 20 -15
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
NDS8958 Rev. C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V
VGS = 0 V, ID = -250 µA
Zero Gate Voltage Drain Current VDS = 24 V, V
VDS = -24 V, V
= 0 V N-Ch 1 µA
GS
TJ = 55°C
= 0 V P-Ch -1 µA
GS
TJ = 55°C
P-Ch -30 V
10 µA
-10 µA Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
All -100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
VDS = VGS, ID = 250 µA
TJ = 125°C
VDS = VGS, ID = -250 µA
TJ = 125°C
VGS = 10 V, ID = 5.3 A
N-Ch 1 1.6 2.8 V
0.7 1.2 2.2
P-Ch -1 -1.6 -2.8
-0.7 -1.2 -2.2
N-Ch 0.033 0.035
TJ = 125°C 0.046 0.063
VGS = 4.5 V, ID = 4.4 A
0.046 0.05
VGS = -10 V, ID = -4.0 A P-Ch 0.052 0.065
TJ = 125°C
0.075 0.13
VGS = -4.5 V, ID = -3.3 A 0.085 0.1
I
D(on)
On-State Drain Current
VGS = 10 V, VDS = 5 V
N-Ch 20 A
VGS = -10 V, VDS = -5 V P-Ch -15
g
FS
Forward Transconductance
VDS = 10 V, ID = 5.3 A
N-Ch 10.5 S
VDS = -10 V, ID = -4.0 A P-Ch 7
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance N-Channel
VDS = 15 V, VGS = 0 V, f = 1.0 MHz
C
oss
C
rss
Output Capacitance N-Ch 370 pF
P-Channel
Reverse Transfer Capacitance N-Ch 250 pF
VDS = -15 V, VGS = 0 V, f = 1.0 MHz
N-Ch 720 pF P-Ch 690
P-Ch 430
P-Ch 160
NDS8958 Rev. C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
D(on)
r
D(off)
f
Turn - On Delay Time N-Channel
VDD = 10 V, ID = 1 A, V
= 10 V, R
Turn - On Rise Time N-Ch 13 30 ns
GEN
GEN
= 6
P-Channel
Turn - Off Delay Time N-Ch 29 50 ns
VDD = -10 V, ID = -1 A, V
= -10 V, R
GEN
GEN
= 6
N-Ch 12 20 ns P-Ch 9 20
P-Ch 20 25
P-Ch 40 50
Turn - Off Fall Time N-Ch 10 20 ns
P-Ch 19 40
Q
g
Q
gs
Q
gd
Total Gate Charge N-Channel
VDS = 10 V, ID = 5.3 A, VGS = 10 V
N-Ch 19 30 nC P-Ch 21 30
Gate-Source Charge N-Ch 2.2
P-Channel
Gate-Drain Charge N-Ch 5.5
VDS = -10 V, ID = -4.0 A, VGS = -10 V
P-Ch 3.1
P-Ch 5.1
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 1.3 A
P-Ch -1.3
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.3 A VGS = 0 V, IS = -1.3 A
(Note 2) N-Ch 0.9 1.2 V
(Note 2)
P-Ch -0.85 -1.2
Reverse Recovery Time VGS = 0 V, IF = 1.3 A, dIF/dt = 100 A/µs N-Ch 100 ns
VGS = 0 V, IF = -1.3 A, dIF/dt = 100 A/µs
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
T
J−TA
θJA
JA
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
1a
J−TA
=
(t)
R
θ
JC
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
2
= I
(t) ×R
DS (ON ) T
D
+R
(t)
θ
CA
J
1b 1c
P-Ch 100
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8958 Rev. C
Typical Electrical Characteristics: N-Channel
25
V =10V
GS
20
15
6.0
5.0
4.5
4.0
2.5
3
2
V = 3.0V
GS
3.5
4.0
3.5
10
5
D
I , DRAIN-SOURCE CURRENT (A)
0
0 0.5 1 1.5 2 2.5 3
V , DRAIN-SOURCE VOLTAGE (V)
DS
3.0
1.5
DS(ON)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.5 0 5 10 15 20 25
I , DRAIN CURRENT (A)
D
Figure 1. N-Channel On-Region Characteristic. Figure 2. N-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
1.6
I = 5.3A
D
1.4
V =10V
GS
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
2
V = 10V
GS
1.75
1.5
1.25
1
DS(ON)
R , NORMALIZED
0.75
DRAIN-SOURCE ON-RESISTANCE
0.5 0 5 10 15 20 25
I , DRAIN CURRENT (A)
D
T = 125°C
J
4.5
5.0
6.0 10
25°C
-55°C
Figure 3. N-Channel On-Resistance Variation with
Temperature.
25
V = 10V
DS
20
15
10
D
I , DRAIN CURRENT (A)
5
0
1 2 3 4 5 6
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J 25°C
125°C
Figure 5. N-Channel Transfer Characteristic.
Figure 4. N-Channel On-Resistance Variation with
Drain Current and Temperature.
1.2
V = V
1.1
1
0.9
th
V , NORMALIZED
0.8
0.7
GATE-SOURCE THRESHOLD VOLTAGE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
DS GS
I = 250µA
D
Figure 6. N-Channel Gate Threshold Variation
with Temperature.
NDS8958 Rev. C
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