Fairchild Semiconductor NDS8936 Datasheet

NDS8936

Dual N-Channel Enhancement Mode Field Effect Transistor

General Description Features

June 1997

These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.

5.3A, 30V. R
R

High density cell design for extremely low R

= 0.035Ω @ V

DS(ON)

= 0.05Ω @ V

DS(ON)

= 10V

GS

= 4.5V.

GS

.

DS(ON)

High power and current handling capability in a widely used
surface mount package.

Dual MOSFET in surface mount package.

________________________________________________________________________________

5

6

7

8

4

3

2

1

Absolute Maximum Ratings T

Symbol Parameter NDS8936 Units

V

DSS

V

GSS

I

D

P

D

TJ,T

THERMAL CHARACTERISTICS

R

θJA

R

θJC

© 1997 Fairchild Semiconductor Corporation

Drain-Source Voltage 30 V

Gate-Source Voltage ± 20 V

Drain Current - Continuous (Note 1a) ± 5.3 A

- Pulsed ± 20

Power Dissipation for Dual Operation 2 W

Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Temperature Range -55 to 150 °C

STG

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

= 25°C unless otherwise noted

A

NDS8936 Rev. G

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV

I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

1 µA

TJ = 55°C

10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 2.8 V

TJ = 125°C 0.7 1.2 2.2

R

DS(ON)

Static Drain-Source On-Resistance

VGS = 10 V, ID = 5.3 A

TJ = 125°C

0.033 0.035

0.046 0.063

Ω

VGS = 4.5 V, ID = 4.4 A 0.046 0.05

0.064 0.09
20 A
10

10.5 S

I

g

D(on)

FS

On-State Drain Current

Forward Transconductance

TJ = 125°C
VGS = 10 V, VDS = 5 V
VGS = 4.5 V, VDS = 5 V
VDS = 10 V, ID = 5.3 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 370 pF

VDS = 15 V, VGS = 0 V,
f = 1.0 MHz

Reverse Transfer Capacitance 250 pF

720 pF

SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A,

V

= 10 V, R

Turn - On Rise Time 13 30 ns

GEN

GEN

= 6 Ω

12 20 ns

Turn - Off Delay Time 29 50 ns
Turn - Off Fall Time 10 20 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 2.2 nC

ID = 5.3 A, VGS = 10 V

19 30 nC

Gate-Drain Charge 5.5 nC

NDS8936 Rev. G

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

t

rr

Notes:

1. R

P

design while R

D

Typical R

Maximum Continuous Drain-Source Diode Forward Current 1.2 A
Drain-Source Diode Forward Voltage

VGS = 0 V, IS = 5.3 A

(Note 2)

0.9 1.3 V

Reverse Recovery Time VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs 100 ns

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

qJA

a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.

b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.

c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.

T

J−TA

=

(t)

R

θJA

θJC+RθCA

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

1a

J−TA

2

= I

(t) ×R

DS (ON ) T

D

(t)

J

1b

1c

is guaranteed by

JC

θ

Scale 1 : 1 on letter size paper.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDS8936 Rev. G