NDS8928
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance and provide superior switching performance. These
devices are particularly suited for low voltage applications such
as notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
N-Channel 5.5A, 20V, R
R
P-Channel -3.8A, -20V, R
R
High density cell design for extremely low R
=0.035Ω @ V
DS(ON)
=0.045Ω @ V
DS(ON)
=0.07Ω @ V
DS(ON)
=0.1Ω @ V
DS(ON)
=4.5V
GS
=2.7V
GS
=-4.5V
GS
=-2.7V.
GS
.
DS(ON)
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward CurrentN-Ch1.3A
P-Ch-1.3
V
SD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.3 A
VGS = 0 V, IS = -1.3 A
(Note 2)
(Note 2)
N-Ch0.81.2V
P-Ch-0.75-1.2
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
(t)
P
D
Typical R
is determined by the user's board design.
CA
θ
T
=
R
θ
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: