Fairchild Semiconductor NDS8434A Datasheet
NDS8434A
Single P-Channel Enhancement Mode Field Effect Transistor
General Description Features
March 1997
SO-8 P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
-7.8 A, -20 V. R
R
High density cell design for extremely low R
= 0.024 Ω @ V
DS(ON)
= 0.032 Ω @ V
DS(ON)
= -4.5 V
GS
= -2.5V.
GS
DS(ON).
High power and current handling capability in a widely used
surface mount package.
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
___________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS8434A Units
V
DSS
V
GSS
I
D
P
D
TJ,T
Drain-Source Voltage -20 V
Gate-Source Voltage ±8 V
Drain Current - Continuous (Note 1a)
- Pulsed
-7.8 A
-25
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1.2
1
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
NDS8434A Rev.D
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current
VDS = -16 V, V
GS
= 0 V
TJ =55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -8 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
D(on)
GS(th)
DS(ON)
FS
Gate Threshold Voltage VDS = VGS, ID = -250 µA -0.4 -0.51 -1 V
TJ = 125°C
-0.3 -0.32 -0.8
Static Drain-Source On-Resistance VGS = -4.5 V, ID = -7.9 A 0.021 0.024
0.032 0.043
0.027 0.032
-25 A
-10
28 S
On-State Drain Current
Forward Transconductance
TJ = 125°C
VGS = -2.5 V, ID = -7.2 A
VGS = -4.5 V, VDS = -5 V
VGS = -2.5 V, VDS = -5 V
VDS = -4.5 V, ID = -7.9 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, V
Output Capacitance 1100 pF
f = 1.0 MHz
GS
= 0 V,
1730 pF
Reverse Transfer Capacitance 300 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 38 70 ns
VDD = -5 V, ID = -1 A,
V
= -4.5 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 210 300 ns
Turn - Off Fall Time 78 150 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 3.8 nC
Gate-Drain Charge 8.2 nC
VDS = -10 V,
ID = -7.9 A, VGS = -4.5 V
13 25 ns
35 55 nC
NDS8434A Rev.D
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current -2.1 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -2.1 A
(Note 2)
-0.64 -1.2 V
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
Typical R
design while R
(t)
P
D
is determined by the user's board design.
CA
θ
T
=
R
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.
J−TA
θJA
1a
T
J−TA
=
(t)
R
+R
θ
JC
2
= I
(t ) ×R
D
(t)
θ
CA
DS(O N ) T
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8434A Rev.D
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