Fairchild Semiconductor NDS8426A Datasheet
NDS8426A
Single N-Channel Enhancement Mode Field Effect Transistor
General Description Features
January 1998
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance and provide superior switching performance.
These devices are particularly suited for low voltage
10.5 A, 20 V. R
R
High density cell design for extremely low R
High power and current handling capability in a widely used
surface mount package.
= 0.0135 Ω @ V
DS(ON)
= 0.016 Ω @ V
DS(ON)
= 4.5 V.
GS
= 2.7 V.
GS
.
DS(ON)
applications such as notebook computer power
management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
___________________________________________________________________________________________
5
6
7
8
4
3
2
1
ABSOLUTE MAXIMUM RATINGS T
= 25°C unless otherwise noted
A
Symbol Parameter NDS8426A Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 20 V
Gate-Source Voltage ±8 V
Drain Current - Continuous (Note 1a) 10.5 A
- Pulsed 30
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1.2
1
THERMAL CHARACTERISTICS
R
θJA
R
θJC
© 1998 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
NDS8426A Rev.B1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current
VDS = 16 V, V
GS
= 0 V
1 µA
TJ= 55°C 10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 8 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
0.4 0.6 1 V
TJ= 125°C 0.3 0.5 0.8
R
I
g
DS(ON)
D(on)
FS
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = 4.5 V, ID = 10.5 A
TJ= 125°C
VGS = 2.7 V, ID = 10 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID = 10.5 A
0.012 0.0135
0.017 0.024
0.014 0.016
30 A
43 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, V
Output Capacitance 890 pF
f = 1.0 MHz
GS
= 0 V,
2150 pF
Reverse Transfer Capacitance 165 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 26 55 ns
VDD = 5 V, ID = 1 A,
V
= 4.5 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 145 220 ns
Turn - Off Fall Time 40 100 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 7 nC
Gate-Drain Charge 8 nC
VDS = 10 V,
ID = 10.5 A, VGS = 4.5 V
11 30 ns
43 60 nC
NDS8426A Rev.B1
ELECTRICAL CHARACTERISTICS (T
TJ−
T
TJ−
T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Continuous Source Diode Current 2.1 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
A
(t)
=
(t)
R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.
1a
A
2
=
R
+R
θ
JC
(t)
= I
× R
DS(ON)@T
D
(t)
θ
CA
J
VGS = 0 V, IS = 2.1 A
1b
(Note 2)
1c
0.6 1.2 V
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8426A Rev.B1
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