Fairchild Semiconductor NDS8410 Datasheet
February 1996
NDS8410
Single N-Channel Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
10A, 30V. R
R
High density cell design for extremely low R
High power and current handling capability in a widely used
surface mount package.
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
____________________________________________________________________________________________
= 0.015Ω @ VGS = 10V
DS(ON)
= 0.020Ω @ VGS = 4.5V.
DS(ON)
DS(ON)
.
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
5
6
7
8
4
3
2
1
Symbol Parameter NDS8410 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage 20 V
Drain Current - Continuous (Note 1a) ± 10 A
- Pulsed ± 50
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1.2
1
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
JC
© 1997 Fairchild Semiconductor Corporation
NDS8410 Rev B2
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ= 55°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 V
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = 10 V, ID = 10 A
VGS = 4.5 V, ID = 9 A
VGS = 10 V, VDS = 5 V
VDS = 10 V, ID = 10 A
0.013 0.015
0.018 0.02
20 A
22 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 800 pF
VDS = 15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 300 pF
1350 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
V
= 10 V, R
Turn - On Rise Time 20 25 ns
GEN
GEN
= 6 Ω
14 30 ns
Turn - Off Delay Time 56 100 ns
Turn - Off Fall Time 31 80 ns
Total Gate Charge VDS = 15 V,
Gate-Source Charge 5.6 nC
ID = 10 A, VGS = 10 V
46 60 nC
Gate-Drain Charge 14 nC
NDS8410 Rev B2
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
θ
design while R
P
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.1 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θ
J C
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
+R
2
= I
(t) × R
DS (ON ) T
D
(t)
θ
CA
J
1a
VGS = 0 V, IS = 10 A
(Note 2)
VGS = 0V, IF = 2.1 A, dIF/dt = 100 A/µs
1b
1c
0.8 1.2 V
80 ns
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8410 Rev B2
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