Fairchild Semiconductor NDS355N Datasheet
NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
March 1996
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMICA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.6A, 30V. R
= 0.125Ω @ VGS = 4.5V.
DS(ON)
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS355N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous 20 V
Drain Current - Continuous (Note 1a) ± 1.6 A
- Pulsed ± 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to -Case (Note 1) 75 °C/W
NDS355N Rev. D1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ=125°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -12 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 2 V
0.5 1.3 1.5
0.125
Static Drain-Source On-Resistance
TJ=125°C
VGS = 4.5 V, ID = 1.6 A
Ω
TJ=125°C 0.25
0.085
3.5 S
I
g
D(ON)
FS
VGS = 10 V, ID = 1.9 A
On-State Drain Current VGS = 4.5 V, VDS = 5 V 6 A
Forward Transconductance
VDS = 5 V, ID = 1.6 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 130 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 20 pF
245 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 14 30 ns
VGS = 10 V, R
GEN
= 6 Ω
15 30 ns
Turn - Off Delay Time 12 25 ns
Turn - Off Fall Time 4 10 ns
Total Gate Charge VDS = 10 V, ID = 1.6 A,
Gate-Source Charge 1 nC
VGS = 5 V
3.5 5 nC
Gate-Drain Charge 2 nC
NDS355N Rev. D1
Loading...