Fairchild Semiconductor NDS352AP Datasheet

NDS352AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

February 1997

These P -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage applications
such as notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are needed in a
very small outline surface mount package.

-0.9 A, -30 V. R
R

= 0.5 Ω @ VGS = -4.5 V

DS(ON)

= 0.3 Ω @ VGS = -10 V.

DS(ON)

Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current
capability.

________________________________________________________________________________

D

G

S

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter NDS352AP Units

V

DSS

V

GSS

I

D

Drain-Source Voltage -30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a)

±0.9 A

- Pulsed ±10

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 0.5 W

(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

STG

0.46

THERMAL CHARACTERISTICS

R

θ

R

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W

JC

NDS352AP Rev.D

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current

VDS = -24 V, V

GS

= 0 V

TJ =125°C

-1 µA

-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS = 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage

VDS = VGS, ID = -250 µA

-0.8 -1.7 -2.5 V

TJ =125°C -0.5 -1.4 -2.2

R

DS(ON)

Static Drain-Source On-Resistance

VGS = -4.5 V, ID = -0.9 A

0.45 0.5

Ω

TJ =125°C 0.65 0.7

0.25 0.3

1.9 S

I
g

D(ON)

FS

VGS = -10 V, ID = -1 A

On-State Drain Current VGS = -4.5 V, VDS = -5 V -2 A

Forward Transconductance

VDS = -5 V, I

= -0.9 A

D

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 88 pF

VDS = -15 V, VGS = 0 V,
f = 1.0 MHz

Reverse Transfer Capacitance 40 pF

135 pF

SWITCHING CHARACTERISTICS (Note 2)

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

Q

g

Q

gs

Q

gd

Turn - On Delay Time VDD = -6 V, ID = -1 A,
Turn - On Rise Time 17 30 ns

VGS = -4.5 V, R

GEN

= 6 Ω

5 10 ns

Turn - Off Delay Time 35 70 ns
Turn - Off Fall Time 30 60 ns
Turn - On Delay Time VDD = -10 V, ID = -1 A,
Turn - On Rise Time

VGS = -10 V, R

GEN

= 50 Ω

Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge 0.5 nC

VDS = -10 V, ID = -0.9 A,
VGS = -4.5 V

8 15
16 30
35 90
30 90

2 3 nC

ns
ns
ns
ns

Gate-Drain Charge 1 nC

NDS352AP Rev.D