Fairchild Semiconductor NDS351AN Datasheet
NDS351AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
April 1997
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
1.2A, 30 V. R
R
= 0.25 Ω @ VGS = 4.5 V
DS(ON)
= 0.16 Ω @ VGS = 10 V.
DS(ON)
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
_________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS351AN Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous 20 V
Maximum Drain Current - Continuous (Note 1a) ± 1.2 A
- Pulsed ± 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
NDS351AN Rev. C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ =125°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 20 VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
D(ON)
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.8 1.7 2 V
0.5 1.3 1.5
0.19 0.25
0.28 0.37
0.125 0.16
3.5 A
1.8 S
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
TJ =125°C
VGS = 4.5 V, ID = 1.2 A
TJ =125°C
VGS = 10 V, ID = 1.4 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID= 1.2 A,
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 100 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 90 pF
125 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 15 30 ns
VGS = 10 V, R
GEN
= 50 Ω
6 15 ns
Turn - Off Delay Time 14 30 ns
Turn - Off Fall Time 18 40 ns
Total Gate Charge VDS = 10 V, ID = 1.2 A,
Gate-Source Charge 0.5 nC
VGS = 4.5 V
1.9 2.7 nC
Gate-Drain Charge 0.9 nC
NDS351AN Rev. C
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