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NDS335N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These N -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.7 A, 20 V. R
R
= 0.14 Ω @ VGS= 2.7 V
DS(ON)
= 0.11 Ω @ VGS= 4.5 V.
DS(ON)
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS335N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 20 V
Gate-Source Voltage - Continuous 8 V
Maximum Drain Current - Continuous (Note 1a) 1.7 A
- Pulsed 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient
(Note 1a)
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
250 °C/W
NDS335 Rev.C
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current
VDS = 16 V, VGS= 0 V
TJ =125°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -8 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
D(ON)
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.5 0.7 1 V
0.3 0.5 0.8
0.084 0.14
0.13 0.25
0.065 0.11
5 A
10
6 S
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = 2.7 V, ID = 1.7 A
VGS = 4.5 V, ID = 1.7 A
VGS = 2.7 V, VDS = 5 V
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, I
= 1.7 A,
D
TJ =125°C
TJ =125°C
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, VGS = 0 V,
Output Capacitance 130 pF
f = 1.0 MHz
240 pF
Reverse Transfer Capacitance 40 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
Turn - On Delay Time
Turn - On Rise Time 29 45 ns
VDD = 5 V, ID = 1 A,
VGS = 4.5 V, R
Gen
= 6 Ω
Turn - Off Delay Time 28 40 ns
Turn - Off Fall Time 8 20 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.5 nC
Gate-Drain Charge 2 nC
VDS = 10 V, ID = 1.7 A,
VGS = 4.5 V
8 20 ns
6.4 9 nC
NDS335 Rev.C