Fairchild Semiconductor NDP7052L, NDB7052L Datasheet
NDP7052L / NDB7052L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
May 1997
These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
75 A, 50 V. R
R
= 0.010 Ω @ VGS= 5 V
DS(ON)
= 0.0075 Ω @ VGS= 10 V.
DS(ON)
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
C
Symbol Parameter NDP7052L NDB7052L Units
V
DSS
V
DGR
V
GSS
I
D
Drain-Source Voltage 50 V
Drain-Gate Voltage (RGS < 1 MΩ)
50 V
Gate-Source Voltage - Continuous ±16 V
- Nonrepetitive (tP < 50 µs)
±25
Drain Current - Continuous 75 A
- Pulsed 225
P
D
Maximum Power Dissipation @ TC = 25°C
150 W
Derate above 25°C 1 W/°C
TJ,T
Operating and Storage Temperature Range -65 to 175 °C
STG
THERMAL CHARACTERISTICS
R
JC
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Case 1 °C/W
Thermal Resistance, Junction-to-Ambient 62.5 °C/W
JA
NDP7052L Rev.B1
Electrical Characteristics (T
= 25°C unless otherwise noted)
C
Symbol Parameter Conditions Min Typ Max Unit
DRAIN-SOURCE AVALANCHE RATINGS (Note)
W
DSS
I
AR
Single Pulse Drain-Source Avalanche Energy VDD = 25 V, ID = 75 A 550 mJ
Maximum Drain-Source Avalanche Current 75 A
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25 o C
VDS = 48 V, V
GS
= 0 V
50 V
0.075
V/oC
250 µA
TJ = 125°C 1 mA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 16 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -16 V, VDS = 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note)
∆V
V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold VoltageTemp.Coefficient
/∆T
J
Gate Threshold Voltage
ID = 250 µA, Referenced to 25 o C
VDS = VGS, ID = 250 µA
TJ = 125°C
Static Drain-Source On-Resistance VGS = 5 V, ID = 37.5 A 0.0085 0.01
-0.005
1 1.3 2 V
0.8 0.85 1.6
V/oC
Ω
TJ = 150°C 0.014 0.018
0.0065 0.0075
69 S
I
g
D(on)
FS
VGS = 10 V, ID = 37.5 A
On-State Drain Current VGS = 5 V, VDS = 10 V 60 A
Forward Transconductance
VDS = 5 V, ID = 37.5 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 1260 pF
Reverse Transfer Capacitance 450 pF
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
4030 pF
SWITCHING CHARACTERISTICS (Note)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 215 400 nS
Turn - Off Delay Time 110 200 nS
VDD = 25 V, ID = 37.5 A,
VGS = 5 V, R
R
= 10 Ω
GS
GEN
= 10 Ω
Turn - Off Fall Time 170 300 nS
g
gs
gd
Total Gate Charge VDS= 24 V
Gate-Source Charge 15 nC
ID = 75 A , VGS = 5 V
Gate-Drain Charge 45 nC
25 50 nS
92 130 nC
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
ISM
V
SD
t
rr
Irr Reverse Recovery Current 2 10 A
Note:
Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0%.
Maximum Continuos Drain-Source Diode Forward Current 75 A
Maximum Pulsed Drain-Source Diode Forward Current 180 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
VGS = 0 V, IS = 37.5 A (Note)
VGS = 0 V, IF = 37.5 A
0.9 1.3 V
40 150 ns
dIF/dt = 100 A/µs
NDP7052L Rev.B1
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