Fairchild Semiconductor FSTU32160MTD, FSTU32160MTDX Datasheet
© 2000 Fairchild Semiconductor Corporation DS500244 www.fairchildsemi.com
May 1999
Revised March 2000
FSTU32160 16-Bit to 32-Bit Multiplexer/Demultipl exer Bus Switch with −2V Undershoot Protection
FSTU32160
16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch
with −2V Undershoot Protection
General Description
The Fairchild Sw itch F STU3 2160 is a 16-b it t o 32- bit hi ghspeed CMOS TTL-compatible multiplexer/demultiplexer
bus switch. The low on resistance of the switch allows
inputs to be connect ed to output s with out ad ding propag ation delay or generating additional ground bounce noise.
The device can be used in app lications where two buses
need to be addresse d simultaneously. The FSTU3 2160 is
designed so that the A Port de multiplexe s into B
1
or B2 or
both. The A and B Ports are “under shoot hardened” with
UHC protection to support an e xtended range to 2.0V
below ground. Fairchi ld’s integ rated U nde rshoot Hard ened
Circuit, UHC senses undershoot at the I/O’s, and responds
by preventing voltage differentials from developing and
turning on the switch.
Two select (SEL
1
, SEL2) inputs provide switch enabl e co n-
trol. When SEL
1
, SEL2 are HIGH, the devic e precharges
the B Port to a selectable bi as voltage (Bias V) to minimize
live insertion noise.
Features
■ Undershoot hardened t o −2V (A and B Ports).
■ Slower Output Enable times prevent signal disruption
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
CC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
■ See Applications Note AN-5008 for details
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
UHC is a trademark of Fairc hild Semiconductor C orporation.
Order Number Package Number Package Description
FSTU32160MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com 2
FSTU32160
Connection Diagram Pin Descriptions
Tr uth Table
Logic Diagram
Pin Name Description
SEL
1
, SEL
2
Select Inputs
ABus A
B
1
, B
2
Bus B
Inputs
Function
SEL
1
SEL
2
LH x A = x B
1
HL x A = x B
2
LLx A = x B1 and x B
2
H H x B1, x B2 = BiasV
Loading...