Fairchild Semiconductor FQU3N60, FQD3N60 Datasheet

FQD3N60 / FQU3N60

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600V N-Channel MOSFET

April 2000

QFET

QFET

QFETQFET

TM

General Description

FQD3N60 / FQU3N60

These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.

D

S

D-PAK

= 25°C)

C

G

D

S



TC = 25°C unless otherwise noted

= 25°C)

C

= 100°C)

C

FQD Series

- Continuous (T

- Continuous (T

- Derate above 25°C 0.4 W/°C

G

Absolute Maximum Ratings

Symbol Parameter FQD3N60 / FQU3N60 Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt
P

D

, T

T

J

STG

T

L

Drain-Source Voltage 600 V
Drain Current

Drain Current - Pulsed
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) *
Power Dissipation (T

Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
1/8from case for 5 seconds

Features

• 2.4A, 600V, R

• Low gate charge ( typical 10 nC)

• Low Crss ( typical 5.5 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

I-PAK

FQU Series

(Note 1)

(Note 2)
(Note 1)
(Note 1)
(Note 3)

= 3.6Ω @VGS = 10 V

DS(on)

G

2.4 A

1.5 A

9.6 A

±

30 V

200 mJ

2.4 A

5.0 mJ

4.5 V/ns

2.5 W
50 W

300 °C

D

S

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θ

JC

R

θ

JA

R

θ

JA

* When mounted on the minimum pad size recommended (PCB Mount)

©2000 Fairchild Semiconductor International

Thermal Resistance, Junction-to-Case -- 2.5 °CW
Thermal Resistance, Junction-to-Ambient * -- 50 °CW
Thermal Resistance, Junction-to-Ambient -- 110 °CW

Rev. A, April 2000

FQD3N60 / FQU3N60

Electrical Characteristics



TC = 25°C unless otherwise noted

Symbol Parameter T e s t Conditions Min Typ Max Units

Off Characteristics

BV

∆

BV
/ ∆T
I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage

DSS

Breakdown Voltage Temperature

DSS

Coefficient

J

Zero Gate Voltage Drain Current
Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 µA

V

GS

= 250 µA, Referenced to 25°C

I

D

V

= 600 V, VGS = 0 V

DS

V

= 480 V, TC = 125°C

DS

= 30 V, VDS = 0 V

V

GS

V

= -30 V, VDS = 0 V

GS

600 -- -- V

-- 0.6 -- V/°C

-- -- 10

-- -- 100

-- -- 100 nA

-- -- -100 nA

On Characteristics

V
R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage
Static Drain-Source

On-Resistance
Forward Transconductance

= VGS, ID = 250 µA

V

DS

= 10 V, ID = 1.2 A

V

GS

= 50 V, ID = 1.2 A

V

DS

(Note 4)

3.0 -- 5.0 V

-- 2.8 3.6

-- 2.4 -- S

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance -- 50 65 pF
Reverse Transfer Capacitance -- 5.5 7.5 pF

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 350 450 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q
Q
Q

g
gs
gd

Turn-On Delay Time
Turn-On Rise Time -- 30 70 ns
Turn-Off Delay Time -- 20 50 ns
Turn-Off Fall Time -- 30 70 ns
Total Gate Charge
Gate-Source Charge -- 2.7 -- nC
Gate-Drain Charge -- 4.9 -- nC

= 300 V, ID = 3.0 A,

V

DD

Ω

= 25

R

G

V

= 480 V, ID = 3.0 A,

DS

V

GS

= 10 V

(Note 4, 5)

(Note 4, 5)

-- 10 30 ns

-- 10 13 nC

µ

A

µ

A

Ω

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 64mH, I

3. ISD  3.0A, di/dt  200A/µs, V

4. Pulse Test : Pulse width 300µs, Duty cycle 2%

5. Essentially independent of operating temperature

©2000 Fairchild Semiconductor International

Maximum Continuous Drain-Source Diode Forward Current -- -- 2.4 A
Maximum Pulsed Drain-Source Diode Forward Current -- -- 9.6 A

= 0 V, IS = 2.4 A

Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge -- 1.2 --

= 2.4A, VDD = 50V, RG = 25

AS

DD



BV

DSS,

Ω,

Starting TJ = 25°C

Starting TJ = 25°C

V

GS

= 0 V, IS = 3.0 A,

V

GS

/ dt = 100 A/µs

dI

F

(Note 4)

-- -- 1.4 V

-- 210 -- ns

µ

Rev. A, April 2000

C

Typical Characteristics

V

GS

Top : 1 5 .0 V

10.0 V

8.0 V

7.0 V

6.5 V

6.0 V

0

Bottom : 5.5 V

10

0

FQD3N60 / FQU3N60

-1

10

, Dra in Curre n t [A ]

D

I

-2

10

-1

10

0

10



Note s :

1. 250s Pulse Test



2. T

= 25

C

1

10

VDS, Drain-Source Voltage [V]

10



25

, Dra in C u rre n t [A]

D

I

-1

10

246810

VGS , Gate-Source Voltage [V]



150



-55



Note s :

= 50V

1. V

DS

2. 250s Pulse Test

Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s

12

10

8

],



[

6

DS(ON)

R

4

Drain-Source On-Resistance

2

0

01234567

VGS = 20V

VGS = 10V



Note : T

ID, Drain Current [A]

0



= 25

J

10



, Reverse Drain Current [A]

DR

I

-1

10

150

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

VSD , Source-Drain Voltage [V]



25



Note s :

= 0V

1. V

GS

2. 250s Pulse Test

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

600

500

400

300

200

Capacitance [pF]

100

0

-1

10

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Ch a ra ct eristics

©2000 Fairchild Semiconductor International

C

iss

C

oss

C

rss

0

10

VDS, Drain-Source Voltage [V]

C

= Cgs + Cgd (Cds = shorted)

iss

C

= Cds + C

oss

gd

C

= C

rss

gd



Note s :

1. V

2. f = 1 MHz

1

10

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

12

10

8

= 0 V

GS

6

4

, Gate-Source Voltage [V]

GS

2

V

0

0246810

QG, Total Gate C h a rge [n C]

VDS = 120V

VDS = 300V

VDS = 480V



= 3.0 A

Note : I

D

Rev. A, April 2000