Fairchild Semiconductor FM25C160U Datasheet

FM25C160U
16K-Bit SPI™ Interface
Serial CMOS EEPROM

FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM

February 2002

General Description

The FM25C160U is a 16K bit serial interface CMOS EEPROM
(Electrically Erasable Programmable Read-Only Memory). This
device fully conforms to the SPI 4-wire protocol which uses Chip
Select (/CS), Clock (SCK), Data-in (SI) and Data-out (SO) pins to
synchronously control data transfer between the SPI microcontroller
and the EEPROM. In addition, the serial interface allows a minimal
pin count, packaging designed to simplify PC board layout re­quirements and offers the designer a variety of low voltage and low
power options.

This SPI EEPROM family is designed to work with the 68HC11 or
any other SPI-compatible, high-speed microcontroller and offers
both hardware (/WP pin) and software ("block write") data protec­tion. For example, entering a 2-bit code into the STATUS REGIS­TER prevents programming in a selected block of memory and all
programming can be inhibited by connecting the /WP pin to VSS;
allowing the user to protect the entire array or a selected section.
In addition, SPI devices feature a /HOLD pin, which allows a
temporary interruption of the datastream into the EEPROM.

Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con­sumption for a continuously reliable non-volatile solution for all
markets.

Block Diagram

/CS

/HOLD

SCK

SI

Instruction

Register

Functions

■ SPI MODE 0 interface

■ 16K bits organized as 2048 x 8

■ Extended 2.7V to 5.5V operating voltage

■ 2.1 MHz operation @ 4.5V - 5.5V

■ Self-timed programming cycle

■ "Programming complete" indicated by STATUS REGISTER

polling

■ /WP pin and BLOCK WRITE protection

Features

■ Sequential read of entire array

■ 16 byte "Page write" mode to minimize total write time per

byte

■ /WP pin and BLOCK WRITE protection to prevent inadvert­ent programming as well as programming ENABLE and
DISABLE opcodes.

■ /HOLD pin to suspend data transfer

■ Typical 1µA standby current (ISB) for "L" devices and 0.1µA

standby current for "LZ" devices.

■ Endurance: Up to 1,000,000 data changes

■ Data retention greater than 40 years

V

Instruction

Decoder

Control Logic

and Clock

Generators

V

/WP

CC

SS

SPI™ is a trademark of Motorola Corporation

© 2002 Fairchild Semiconductor Corporation

FM25C160U Rev. B

Address
Counter/
Register

Decoder

Program
Enable

V

EEPROM Array

Read/Write Amps

Data In/Out Register

8 Bits

Non-Volatile

Status Register

1

PP

High Voltage

Generator

and

Program

Timer

Data Out

Buffer

SO

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Connection Diagram

FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM

Dual-In-Line Package (N) and SO Package (M8)

Pin Names

/CS

SO

1

2

V

8

7

CC

/HOLD

FM25C160U

/WP

V

SS

3

4

SCK

6

SI

5

Top View

See Package Number N08E (N) and M08A (M8)

/CS Chip Select Input

SO Serial Data Output

/WP Write Protect

V

SS

SI Serial Data Input

SCK Serial Clock Input

/HOLD Suspends Serial Data

V

CC

Ground

Power Supply

Ordering Information

FM 25 C XX U LZ E XX Letter Description

Package N 8-pin DIP

M8 8-pin SO

Temp. Range None 0 to 70°C

Voltage Operating Range Blank 4.5V to 5.5V

Density/Mode 160 16K, mode 0

Interface 25 SPI

V -40 to +125°C
E -40 to +85°C

L 2.7V to 5.5V
LZ 2.7V to 5.5V and

<1µA Standby Current

Ultralite CS100UL Process

C CMOS technology

FM Fairchild Nonvolatile

Memory Prefix

FM25C160U Rev. B

2

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Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications

FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltage with

Respect to Ground +6.5V to -0.3V

Lead Temp. (Soldering, 10 sec.) +300°C

Operating Conditions

Ambient Operating Temperature

FM25C160U 0°C to +70°C
FM25C160UE -40°C to +85°C
FM25C160UV -40°C to +125°C

Power Supply (VCC) 4.5V to 5.5V

ESD Rating 2000V

DC and AC Electrical Characteristics 4.5V ≤ V

≤ 5.5V (unless otherwise specified)

CC

Symbol Parameter Conditions Min Max Units

I

I

CCSB

I

V

V

V

V

f

t

t

t

CLH

t

CLL

t

CSH

t

CSS

t

DIS

t

HDS

t

CSN

t

DIN

t

HDN

t

t

t

t

t

t

WP

CC

I

OL

OP

PD

DH

DF

HZ

IL

IL

IH

OL

OH

RI

FI

LZ

Operating Current /CS = V

Standby Current /CS = V

IL

CC

Input Leakage VIN = 0 to V

Output Leakage V

= GND to V

OUT

CC

CC

-1 +1 µA

-1 +1 µA

3mA

50 µA

CMOS Input Low Voltage -0.3 VCC * 0.3 V

CMOS Input High Voltage 0.7 * V

CCVCC

+ 0.3 V

Output Low Voltage IOL = 1.6 mA 0.4 V

Output High Voltage IOH = -0.8 mA VCC - 0.8 V

SCK Frequency 2.1 MHz

Input Rise Time 2.0 µs

Input Fall Time 2.0 µs

Clock High Time (Note 2) 190 ns

Clock Low Time (Note 2) 190 ns

Min /CS High Time (Note 3) 240 ns

/CS Setup Time 240 ns

Data Setup Time 100 ns

/HOLD Setup Time 90 ns

/CS Hold Time 240 ns

Data Hold Time 100 ns

/HOLD Hold Time 90 ns

Output Delay CL = 200 pF 240 ns

Output Hold Time 0 ns

/HOLD to Output Low Z 100 ns

Output Disable Time CL = 200 pF 240 ns

/HOLD to Output High Z 100 ns

Write Cycle Time 1–16 Bytes 10 ms

Capacitance T

Symbol Test Typ Max Units

C

OUT

C

IN

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, t
example, for a fOP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then t

Note 3: /CS must be brought high for a minimum of t

Note 4: This parameter is periodically sampled and not 100% tested.

FM25C160U Rev. B

= 25°C, f = 2.1/1 MHz (Note 4)

A

Output Capacitance 3 8 pF

Input Capacitance 2 6 pF

between consecutive instruction cycles.

CSH

AC Test Conditions

Output Load CL = 200 pF

Input Pulse Levels 0.1 * VCC – 0.9 * V

Timing Measurement Reference Level 0.3 * VCC - 0.7 * V

+ t

must be equal to or greater than 1/fOP. For

CLH

must be set to a minimum of 286ns.

CLL

3

CLL

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CC

CC

Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications

FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM

Absolute Maximum Ratings (Note 5)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltage with

Respect to Ground +6.5V to -0.3V

Lead Temp. (Soldering, 10 sec.) +300°C

ESD Rating 2000V

DC and AC Electrical Characteristics 2.7V ≤ V

Operating Conditions

Ambient Operating Temperature

FM25C160UL/LZ 0°C to +70°C
FM25C160ULE/LZE -40°C to +85°C
FM25C160ULV -40°C to +125°C

Power Supply (V

≤ 4.5V (unless otherwise specified)

CC

) 2.7V–4.5V

CC

25C160UL/LE 25C160ULV

25C160ULZ/ZE

Symbol Parameter Part Conditions Min. Max. Min Max Units

I

CC

I

CCSB

I

IL

I

OL

V

IL

V

IH

V

OL

V

OH

f

OP

t

RI

t

FI

t

CLH

t

CLL

t

CSH

t

CSS

t

DIS

t

HDS

t

CSN

t

DIN

t

HDN

t

PD

t

DH

t

LZ

t

DF

t

HZ

t

WP

Operating Current /CS = V
Standby Current L /CS = V

LZ 1 N/A µA

IL

CC

Input Leakage VIN = 0 to V

Output Leakage V

= GND to V

OUT

CC

-1 1 -1 1 µA

-1 1 -1 1 µA

CC

33mA

10 10 µA

Input Low Voltage -0.3 VCC * 0.3 -0.3 VCC * 0.3 V

Input High Voltage VCC * 0.7 VCC + 0.3 VCC * 0.7 VCC + 0.3 V

Output Low Voltage I

Output High Voltage I

= 0.8 mA 0.4 0.4 V

OL

= –0.8 mA VCC - 0.8 VCC - 0.8 V

OH

SCK Frequency 1.0 1.0 MHz

Input Rise Time 2.0 2.0 µs

Input Fall Time 2.0 2.0 µs

Clock High Time (Note 6) 410 410 ns

Clock Low Time (Note 6) 410 410 ns

Min. /CS High Time (Note 7) 500 500 ns

/CS Setup Time 500 500 ns

Data Setup Time 100 100 ns

/HOLD Setup Time 240 240 ns

/CS Hold Time 500 500 ns

Data Hold Time 100 100 ns

/HOLD Hold Time 240 240 ns

Output Delay CL = 200 pF 500 500 ns

Output Hold Time 0 0 ns

/HOLD Output Low Z 240 240 ns

Output Disable Time CL = 200 pF 500 500 ns

/HOLD to Output Hi Z 240 240 ns

Write Cycle Time 1-16 Bytes 15 15 ms

Capacitance T

Symbol Test Typ Max Units

C

OUT

C

IN

Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, t
example, for a fOP of 1MHz, the period equals 1000ns. In this case if t

Note 7: /CS must be brought high for a minimum of t

Note 8: This parameter is periodically sampled and not 100% tested.

FM25C160U Rev. B

= 25°C, f = 2.1/1 MHz (Note 8)

A

Output Capacitance 3 8 pF

Input Capacitance 2 6 pF

= is set to 410ns, then t

between consecutive instruction cycles.

CSH

CLH

AC Test Conditions

Output Load CL = 200pF

Input Pulse Levels 0.1 * VCC - 0.9 * V

Timing Measurement Reference Level 0.3 * VCC - 0.7 * V

+ t

must be equal to or greater than 1/fOP. For

CLH

must be set to a minimum of 590ns.

CLL

4

CLL

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CC

CC