Fairchild Semiconductor FDS6162N3 Datasheet
May 2003
FDS6162N3
20V N-Channel PowerTrench MOSFET
FDS6162N3
General Description
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
“low side” synchronous rectifier operation, providing an
extremely low R
in a small package.
DS(ON)
Applications
• Synchronous rectifier
• DC/DC converter
Features
• 21 A, 20 V R
R
• High performance trench technology for extremely
DS(ON)
low R
• High power and current handling capability
• Fast switching
• FLMP SO-8 package: Enhanced thermal
performance in industry-standard package size
= 4.5 mΩ @ VGS = 4.5 V
DS(ON)
= 6.0 mΩ @ VGS = 2.5 V
DS(ON)
Bottom-side
Drain Contact
45
36
27
18
Absolute Maximum Ratings T
o
=25
C unless otherwise noted
A
Symbol Parameter Ratings Units
V
Drain-Source Voltage 20 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1a) 21 A
– Pulsed 60
PD
TJ, T
STG
Power Dissipation
Operating and Storage Junction Temperature Range –55 to +150
(Note 1a) 3.0
± 12
V
W
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 40
0.5
°C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6162N3 FDS6162N3 13’’ 12mm 2500 units
2002 Fairchild Semiconductor Corpora tion
FDS6162N3 Rev B2 (W)
FDS6162N3
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
J
I
Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1
DSS
I
Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
GSSF
I
Gate–Body Leakage, Reverse VGS = –12 V , VDS = 0 V –100 nA
GSSR
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
20
13
V
mV/°C
µA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
= VGS, ID = 250 µA
V
DS
= 250 µA, Referenced to 25°C
I
D
VGS = 4.5 V, ID = 21 A
= 2.5 V, ID = 18 A
V
GS
= 4.5 V, ID = 21 A, TJ = 125°C
V
GS
gFS Forward Transconductance VDS = 5 V, ID = 21 A 119 S
0.6 0.9 1.5 V
–4
3.3
4.3
4.8
4.5
6.0
7.2
mV/°C
mΩ
Dynamic Characteristics
C
Input Capacitance 5521 pF
iss
C
Output Capacitance 1473 pF
oss
C
Reverse Transfer Capacitance
rss
RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 1.3
V
= 10 V, V
DS
f = 1.0 MHz
= 0 V,
GS
706 pF
Ω
Switching Characteristics (Note 2)
= 10 V, ID = 1 A,
V
t
Turn–On Delay Time 20 32 ns
d(on)
tr Turn–On Rise Time 25 40 ns
t
Turn–Off Delay Time 85 136 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 52 73 nC
Qgs Gate–Source Charge 9 nC
Qgd Gate–Drain Charge
DD
= 4.5 V, R
V
GS
= 10 V, ID = 21 A,
V
DS
= 4.5 V
V
GS
GEN
= 6 Ω
55 88 ns
14.5 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current 2.5 A
VSD
Drain–Source Diode Forward
Voltage
trr Diode Reverse Recovery Time 42 nS
Qrr Diode Reverse Recovery Charge
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
is guaranteed by design while R
θJC
is determined by the user's board design.
θCA
= 0 V, IS = 2.5 A (Note 2)
V
GS
= 21 A,
I
F
= 100 A/µs
d
iF/dt
0.6 1.2 V
52 nC
a) 40°C/W when
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
mounted on a 1in
of 2 oz copper
2
pad
b) 85°C/W when mounted on
a minimum pad of 2 oz
copper
FDS6162N3 Rev B2 (W)
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