Fairchild Semiconductor FDC6320C Datasheet
October 1997
FDC6320C
Dual N & P Channel , Digital FET
General Description Features
These dual N & P Channel logic level enhancement mode field
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage
applications as a replacement for bipolar digital transistors in
load switching applications. Since bias resistors are not
required, this dual digital FET can replace several digital
transistors with difference bias resistors.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
N-Ch 25 V, 0.22 A, R
P-Ch 25 V, -0.12 A, R
= 5 Ω @ VGS= 2.7 V.
DS(ON)
= 13 Ω @ VGS= -2.7 V.
DS(ON)
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
SO-8
SOT-223
SOIC-16
Absolute Maximum Ratings T
4
5
6
= 25oC unless other wise noted
A
3
2
1
Symbol Parameter N-Channel P-Channel Units
V
, VCCDrain-Source Voltage, Power Supply Voltage 25 -25 V
DSS
V
ID, I
GSS
Gate-Source Voltage, 8 -8 V
, V
IN
Drain/Output Current - Continuous 0.22 -0.12 A
O
- Pulsed 0.5 -0.5
P
D
Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b) 0.7
TJ,T
ESD Electrostatic Discharge Rating MIL-STD-883D
Operating and Storage Tempature Ranger -55 to 150 °C
STG
6 kV
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
© 1997 Fairchild Semiconductor Corporation
FDC6320C.Rev C
DMOS Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 25 V
VGS = 0 V, ID = -250 µA
∆BV
DSS
Breakdown Voltage Temp. Coefficient ID= 250 µA, Referenced to 25 oC N-Ch 25 mV /oC
/∆T
J
ID = -250 µA, Referenced to 25 oC
I
DSS
I
DSS
I
GSS
Zero Gate Voltage Drain Current VDS= 20 V, VGS= 0 V, N-Ch 1 µ A
Zero Gate Voltage Drain Current
Gate - Body Leakage Current
VDS =-20 V, V
VGS = 8 V, VDS= 0 V
VGS = -8 V, VDS= 0 V P-Ch -100 nA
ON CHARACTERISTICS (Note 2)
∆V
GS(th)
Gate Threshold Voltage Temp. Coefficient
/∆T
J
ID = 250 µA, Referenced to 25 o C
ID= -250 µA, Referenced to 25 o C P-Ch 1.9
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID= 250 µA
VDS = VGS, ID= -250 µA P-Ch -0.65 -1 -1.5
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 2.7 V, ID = 0.2 A
VGS = 4.5 V, ID = 0.4 A
VGS = -2.7 V, ID = -0.05 A
VGS = -4.5 V, ID = -0.2 A
I
D(ON)
On-State Drain Current
VGS = 2.7 V, VDS = 5 V
VGS = -2.7 V, VDS = -5 V
g
FS
Forward Transconductance
VDS = 5 V, ID= 0.4 A
VDS = -5 V, ID= -0.2 A
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance N-Channel
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
C
oss
C
rss
Output Capacitance N-Ch 6 pF
P-Channel
Reverse Transfer Capacitance N-Ch 1.3 pF
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
GS
= 0 V,
Min Typ Max Units
Type
P-Ch -25
P-Ch -20
TJ = 55°C 10
P-Ch -1 µA
TJ = 55°C -10
N-Ch 100 nA
N-Ch -2.1
N-Ch 0.65 0.85 1.5 V
N-Ch 3.8 5
TJ =125°C
6.3 9
3.1 4
P-Ch 10.6 13
TJ =125°C
15 21
7.9 10
N-Ch 0.2 A
P-Ch -0.05
N-Ch 0.2 S
P-Ch 0.135
N-Ch 9.5 pF
P-Ch 11
P-Ch 7
P-Ch 1.4
mV / oC
Ω
FDC6320C.Rev C
DMOS Electrical Characteristics (T
Symbol Parameter Conditions
= 25 OC unless otherwise noted )
A
Type
Min Typ Max Units
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
Turn - On Delay Time N-Channel N-Ch 5 11 nS
VDD = 6 V, ID = 0.5 A, P-Ch 6 12
t
r
Turn - On Rise Time
VGS = 4.5 V, R
= 50 Ω
GEN
N-Ch 4.5 10 nS
P-Ch 6 12
t
D(off)
Turn - Off Delay Time P-Channel N-Ch 4 10 nS
VDD = -6 V, ID = -0.5 A, P-Ch 7.4 15
t
f
Turn - Off Fall Time
V
GEN
= -4.5 V, R
= 50 Ω
GEN
N-Ch 3.2 8 nS
P-Ch 4 10
Q
g
Total Gate Charge N-Channel
VDS = 5 V,
ID = 0.2 A, VGS = 4.5 V
Q
gs
Q
gd
Gate-Source Charge N-Ch 0.105 nC
P-Channel
Gate-Drain Charge N-Ch 0.045 nC
VDS = -5 V,
ID = -0.2A, VGS = -4.5 V
N-Ch 0.29 0.4 nC
P-Ch 0.23 0.32
P-Ch 0.12
P-Ch 0.03
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 0.5 A
P-Ch -0.5
V
SD
Notes:
1. R
design while R
Typical R
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
is determined by the user's board design.
CA
θ
using the board layouts shown below on FR-4 PCB in a still air environment:
JA
θ
VGS = 0 V, IS = 0.5 A
VGS = 0 V, IS = -0.5 A
(Note 2)
(Note 2) P-Ch -1 -1.3
N-Ch 0.97 1.3 V
is guaranteed by
JC
θ
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
FDC6320C.Rev C
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