Fairchild Semiconductor FDC6312P Datasheet
FDC6312P
Dual P-Channel 1.8V PowerTrench
Specified MOSFET
FDC6312P
January 2001
General Description
These P-Channel 1.8V specified MOSFETs are
produced using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored
to minimize on-state resistance and yet maintain low
gate charge for superior switching performance.
Applications
• Power management
• Load switch
Features
• –2.3 A, –20 V. R
• High performance trench technology for extremely
low R
DS(ON)
• SuperSOTTM-6 package: small footprint (72%
smaller than standard SO-8); low profile (1mm thick)
= 115 mΩ @ VGS = –4.5 V
DS(ON)
R
= 155 mΩ @ VGS = –2.5 V
DS(ON)
= 225 mΩ @ VGS = –1.8 V
R
DS(ON)
D2
D1
S1
4
5
3
2
G2
SuperSOT -6
TM
S2
G1
Absolute Maximum Ratings T
=25oC unless otherwise noted
A
6
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
STG
Drain-Source Voltage –20 V
Gate-Source Voltage
Drain Current – Continuous (Note 1a) –2.3 A
– Pulsed –7
Power Dissipation for Single Operation (Note 1a) 0.96
(Note 1b)
(Note 1c)
Operating and Storage Junction Temperature Range -55 to +150
±8
0.9
0.7
V
W
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient (Note 1a) 130
Thermal Resistance, Junction-to-Case (Note 1) 60
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
.312 FDC6312P 13’’ 12mm 3000 units
2001 Fairchild Semiconductor Corporation
°C/W
°C/W
FDC6312P Rev C (W)
FDC6312P
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
J
I
DSS
I
GSSF
I
GSSR
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
= 0 V, ID = –250 µA
V
GS
I
= –250 µA,Referenced to 25°C
D
Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1
Gate–Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –8 V, VDS = 0 V –100 nA
–20 V
–11
mV/°C
On Characteristics (Note 2)
V
GS(th)
∆VGS(th)
∆T
J
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
= VGS, ID = –250 µA
V
DS
I
= –250 µA,Referenced to 25°C
D
VGS = –4.5 V, ID = –2.3 A
= –2.5 V, ID = –1.9 A
V
GS
= –1.8 V, ID = –1.6 A
V
GS
=–4.5 V, ID =–2.3A, TJ=125°C
V
GS
On–State Drain Current VGS = –4.5 V, VDS = –5 V –7 A
Forward Transconductance VDS = –5 V, ID = –3.5 A 5.3 S
–0.4 –0.9 –1.5 V
2
92
116
166
112
115
155
225
150
mV/°C
mΩ
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 467 pF
Output Capacitance 85 pF
Reverse Transfer Capacitance
= –10 V, V
V
DS
f = 1.0 MHz
GS
= 0 V,
38 pF
Switching Characteristics (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn–On Delay Time 8 16 ns
Turn–On Rise Time 13 23 ns
= –10 V, ID = –1 A,
V
DD
= –4.5 V, R
V
GS
GEN
= 6 Ω
Turn–Off Delay Time 18 32 ns
Turn–Off Fall Time
Total Gate Charge 4.4 7 nC
Gate–Source Charge 1.0 nC
V
= –10 V, ID = –2.3 A,
DS
= –4.5 V
V
GS
Gate–Drain Charge
816ns
0.8 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
Maximum Continuous Drain–Source Diode Forward Current –0.8 A
Drain–Source Diode Forward
Voltage
is guaranteed by design while R
θJC
θCA
V
= 0 V, IS = –0.8 A (Note 2) –0.7 –1.2 V
GS
is determined by the user's board design.
µA
a) 130 °C/W when
mounted on a 0.125
in2 pad of 2 oz.
copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
b) 140°/W when mounted
on a .004 in2 pad of 2 oz
copper
c) 180°/W when mounted on a
minimum pad.
FDC6312P Rev C (W)
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