Fairchild Semiconductor FDC6301N Datasheet

July 1997

FDC6301N
Dual N-Channel , Digital FET

General Description Features

These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild 's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for digital transistors. Since bias
resistors are not required, these N-Channel FET's can replace
several digital transistors, with a variety of bias resistors.

SOT-23

SuperSOTTM-6

Mark: .301

SuperSOTTM-8

4

5

6

25 V, 0.22 A continuous, 0.5 A Peak.

R

= 5 Ω @ VGS= 2.7 V

R

DS(ON)

= 4 Ω @ VGS= 4.5 V.

DS(ON)

Very low level gate drive requirements allowing direct
operation in 3V circuits. V

GS(th)

< 1.5V.

Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.

SO-8

SOT-223

INVERTER APPLICATION

3

SOIC-16

D

2

IN

SG

1

Vcc

OUT

GND

Absolute Maximum Ratings T

= 25oC unless other wise noted

A

Symbol Parameter FDC6301N Units

V

, VCCDrain-Source Voltage, Power Supply Voltage 25 V

DSS

V

, VINGate-Source Voltage, V

GSS

ID, I

Drain/Output Current - Continuous 0.22 A

OUT

IN

8 V

- Pulsed 0.5

P

D

TJ,T
ESD Electrostatic Discharge Rating MIL-STD-883D

Maximum Power Dissipation (Note 1a)
(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

STG

0.9 W

0.7

6.0 kV

Human Body Model (100pf / 1500 Ohm)

THERMAL CHARACTERISTICS

R

θJA

R

θJC

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W

FDC6301N Rev.C

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV

∆BV

I

DSS

I

GSS

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 25 V
Breakdown Voltage Temp. Coefficient

/∆T

J

Zero Gate Voltage Drain Current

ID = 250 µA, Referenced to 25 o C
VDS = 20 V, V

GS

= 0 V

25

1 µA

TJ = 55°C

Gate - Body Leakage Current VGS = 8 V, VDS= 0 V 100 nA

mV /oC

10 µA

ON CHARACTERISTICS (Note 2)

∆V

V
R

GS(th)

DS(ON)

GS(th)

Gate Threshold Voltage Temp.Coefficient

/∆T

J

Gate Threshold Voltage

ID = 250 µA, Referenced to 25 o C
VDS = VGS, ID = 250 µA

Static Drain-Source On-Resistance VGS = 2.7 V, ID = 0.2 A 3.8 5

TJ =125°C

-2.1

mV /oC

0.65 0.85 1.5 V

6.3 9

Ω

VGS = 4.5 V, ID = 0.4 A 3.1 4
I
g

D(ON)

FS

On-State Drain Current

VGS = 2.7 V, VDS = 5 V

Forward Transconductance VDS = 5 V, ID= 0.4 A 0.25 S

0.2 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 6 pF

VDS = 10 V, VGS = 0 V,

f = 1.0 MHz

Reverse Transfer Capacitance 1.3 pF

9.5 pF

SWITCHING CHARACTERISTICS (Note 2)

t

D(on)

t

r

t

D(off)

t

f

Q

g

Q

gs

Q

gd

Inverter Electrical Characteristics (T

I

O (off)

VI

(off)

VI

(on)

R

O (on)

Notes:

1. R

JA

θ

design while R

Turn - On Delay Time VDD = 6 V, ID = 0.5 A,
Turn - On Rise Time 4.5 10 ns

VGS = 4.5 V, R

GEN

= 50 Ω

5 10 ns

Turn - Off Delay Time 4 8 ns
Turn - Off Fall Time 3.2 7 ns
Total Gate Charge VDS = 5 V, ID = 0.2 A,
Gate-Source Charge 0.22 nC

VGS = 4.5 V

0.49 0.7 nC

Gate-Drain Charge 0.07 nC

= 25°C unless otherwise noted)

A

Zero Input Voltage Output Current

VCC = 20 V, VI = 0 V

Input Voltage VCC = 5 V, IO = 10 µA 0.5 V

VO = 0.3 V, IO = 0.005 A

1 V

Output to Ground Resistance VI = 2.7 V, IO = 0.2 A 3.8 5

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design. R

CA

θ

shown below for single device operation on FR-4 in still air.

JA

θ

1 µA

is guaranteed by

JC

θ

Ω

a. 140OC/W on a 0.125 in2 pad of

2oz copper.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

b. 180OC/W on a 0.005 in2 of pad

of 2oz copper.

FDC6301N Rev.C