Fairchild Semiconductor FAN6550 Datasheet

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FAN6550

2A DDR Bus Termination Regulator

Features

• Can source and sink up to 2A continous, 3A peak

• No heatsink required

• Integrated Power MOSFETs

• Generates termination voltages for DDR SDRAM

•V

• Separate voltages for V

• Buffered V

•V

input available for external voltage divider

REF

output

REF

of ±3% or less at 2A

OUT

CCQ

and PV

DD

• Minimum external components

• 0°C to 70°C operating range

• Shutdown for standby or suspend mode operation

• Thermal Shutdown ≈ 130ºC

Block Diagram

Description

The FAN6550 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for DDR SDRAM memory. The FAN6550 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the V 50% of the voltage applied to V be used to produce various user-deﬁned voltages by forcing a voltage on the VREF follows the input VREF is capable of sourcing or sinking up to 2A of current while regulating an output V Transient output currents of ±3A can also be accommodated.

The FAN6550 can also be used in conjunction with series termination resisitors to provide an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs.

pin is open, the FAN6550 output voltage is

REF

pin. In this case, the output voltage

IN

voltage. The switching regulator

IN

voltage to within 3% or less.

TT

. The FAN6550 can also

CCQ

11

13

200kΩ

VREF

200kΩ

AGND

D

GND

9

S

R

12

V

DD

Q

SHDN

2

4 58

PV

P

GND1

DD1

7

PV

DD2

V

L1

(V

)

OUT

3

6

V

L2

(V

)

OUT

P

GND2

15

IN

V

CCQ

10

16

–

+

V

FB

AV

REF

14

CC

BUFFER

+

–

VREF

OUT

OSCILLATOR/

RAMP

GENERATOR

ERROR AMP

1

V

DD

–

+

RAMP COMPARATOR

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FAN6550 PRODUCT SPECIFICATION

Pin Conﬁguration

FAN6550

16-Pin SOIC (M16)

PV

P

GND1

P

GND2

PV

D

V

DD

DD1

V

DD2

GND

L1

L2

1

2

3

4

5

6

7

8

TOP VIEW

16

15

14

13

12

11

10

9

Pin Description

Pin Name Function

1V

2PV

3V

4P

5P

6V

7PV

8D

9V

10 V

DD

DD1

L1

GND1

GND2

L2

DD2

GND

DD

FB

11 VREF

12 SHDN Shutdown active low. CMOS input level

13 AGND Ground for internal reference voltage divider

14 VREF

15 V

16 AV

CCQ

CC

Digital supply voltage

Voltage supply for internal power transistors

Output voltage/ inductor connection

Ground for output power transistors

Output voltage/inductor connection

Voltage supply for internal power transistors

Digital ground

Digital supply voltage

Input for external compensation feedback

Input for external reference voltage

IN

Reference voltage output

OUT

Voltage reference for internal voltage divider

Analog voltage supply

AV

CC

V

CCQ

VREF

AGND

SHDN

VREF

V

FB

V

DD

OUT

IN

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∆

PRODUCT SPECIFICATION FAN6550

Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.

Parameter Min. Max. Units

PV

DD

Voltage on Any Other Pin GND – 0.3 V

Average Switch Current (I

) 2.0 A

AVG

4.5 V

+ 0.3 V

IN

Junction Temperature 150 °C

Storage Temperature Range -65 150 °C

Lead Temperature (Soldering, 10 sec) 300 °C

Thermal Resistance ( θ

)30°C/W

JA

Output Current, Source or Sink (peak) 3.0 A

Operating Conditions

Parameter Min. Max. Units

Temperature Range 0 70 °C

PV

Operating Range 2.0 4.0 V

DD

V

Operating Range 1.4 4.0 V

CCQ

Electrical Characteristics

Unless otherwise speciﬁed, AV

Symbol Parameter Conditions Min. Typ. Max. Units

Switching Regulator

V

TT

Output Voltage, V (See Figure 1)

VREF

Z

IN

Internal Resistor Divider I

OUT

V

Reference Pin Input

REF

Impedance

Switching Frequency 650 kHz

V

OFFSET

Offset Voltage V

Supply

I

Q

Quiescent Current I

Buffer

I

REF

Notes

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

2. AV

CC

Output Load Current 3 mA

, PV

= 3.3V ±10%

DD

= V

CC

TT

– VREF

TT

DD

= PV

OUT

= 3.3V ±10%, TA = Operating Temperature Range (Note 1)

DD

I

= 0,

OUT

V

= open

REF

Note 2

I

= ±2A,

OUT

V

= open

REF

Note 2

= 0

OUT

Note 2

Note 2 V

V

= 2.5V No Load V

CCA

= 0, no load

OUT

V

= 2.5V

CCQ

V

= 2.3V 1.12 1.15 1.18 V

CCQ

V

= 2.5V 1.22 1.25 1.28 V

CCQ

V

= 2.7V 1.32 1.35 1.38 V

CCQ

V

= 2.3V 1.09 1.15 1.21 V

CCQ

V

= 2.5V 1.19 1.25 1.31 V

CCQ

V

= 2.7V 1.28 1.35 1.42 V

CCQ

V

= 2.3V 1.139 1.15 1.162 V

CCQ

V

= 2.5V 1.238 1.25 1.263 V

CCQ

V

= 2.7V 1.337 1.35 1.364 V

CCQ

= 0 100 k Ω

CCQ

= 2.5 –20 20 mV

CCQ

I

VCCQ

I

AVCC

I

SD 0.2 0.5 mA

AVCC

I

VDD

I

SD 0.2 1.0 mA

VDD

I

PVDD

610µA

0.5 1.0 mA

0.25 1.0 mA

100 250 µA

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4

FAN6550 PRODUCT SPECIFICATION

Functional Description

The FAN6550 integrates two power MOSFETs that can be used to source and sink 2A of current while maintaining a tight voltage regulation. Using the external feedback, the output can be regulated well within 3% or less, depending on the external components chosen. Separate voltage supply inputs have been added to accommodate applications with various power supplies for the databus and power buses.

Outputs

The output voltage pins (V address, or clock lines via an external inductor. See the Applications section for recommendations. Output voltage is determined by the V

Inputs

The input voltage pins (V output voltages (V the VREF V

CCQ

IN

input. V

databus.

Output voltage can also be selected by forcing a voltage at the VREF

IN

voltage at the VREF used this case to produce a wide variety of output voltages between 2.3V to 4V.

L1

pin is ﬂoating, the output voltage is 50% of the

can be the reference voltage for the

CCQ

pin. In this case, the output voltage follows the

IN

, V

) are tied to the databus,

L1

L2

or VREF

CCQ

or VREF

CCQ

or V

) . In the default mode, where

L2

inputs.

IN

) determine the

IN

input. Simple voltage dividers can be

VREF Input and Output

The VREF outputs (Inputs section, above). The VREF output pin that is driven by a small output buffer to provide the V buffer is capable of driving several output loads. The output buffer can handle 3mA.

input can be used to force a voltage at the

IN

signal to other devices in the system. The output

REF

OUT

pin is an

Other Supply Voltages

Several inputs are provide for the supply voltages: PV PV

, AV

DD1

, and V

CC

and PV

DD2

The PV power MOSFETs. V digital sections, while AV

.

DD

provide the power supply to the

DD2

provides the voltage supply to the

DD

supplies the voltage for the

CC

analog sections. Again, see the Applications section for recommendations.

DD1

,

Feedback Input

The VFB pin is an input that can be used for closed loop compensation. This input is derived from the voltage output. See application section for recommendation.

TPI

V

TT

TO SDRAMS

C1 820µF F2V OS-CON

L1 3.3µH

C2

0.1µF

R1 100Ω

C3 0.1µF

C4 0.1µF

R2 100Ω

1

V

2

PV

3

V

4

P

5

P

6

V

7

PV

8

D

R4 100kΩ

R5 1kΩ

Figure 1.

C9 0.1µF

U1

FAN6550

DD

DD1

L1

GND1

GND2

L2

DD2

GND

C7 1nF

VREF

AV

CC

V

CCQ

OUT

AGND

SHDN

V

FB

V

DD

C8 0.1µF

R3

100kΩ

16

15

14

13

12

11

IN

10

9

V

CCQ

VREF

SHDN

VREF

OUT

IN

2.5V TO 4V

C5

470µF

GNDGND

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