Fairchild Semiconductor DM7476N, DM7476CW Datasheet

© 2000 Fairchild Semiconductor Corporation DS006528 www.fairchildsemi.com

September 1986
Revised February 2000

DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

DM7476
Dual Master-Slave J-K Flip-Flops with

Clear, Preset, and Complementary Outputs

General Description

This device contains two inde pendent positive pulse trig­gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop afte r a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is tra nsferred to the master. While
the clock is HIGH the J and K inpu ts are disabled. On the

negative transition of th e cl oc k, the da ta fr om the ma ster i s
transferred to the slave. The logic state of J and K input s
must not be allowed to change whi le the clock is HIGH.
The data is transferred to the outputs on the falling edge of
the clock pulse. A LOW logic le vel on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.

Ordering Code:

Connection Diagram Function Table

H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level



= Positive pulse data. The J and K inputs must be held constant while

the clock is HIGH. D ata is transferred to the outpu ts on the falling
edge of the clock pulse.

Q

0

= Th e output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on

each complete active HIGH level clock pulse.

Note 1: This configuration is n onstabl e; tha t is, it will no t pers ist wh en the
preset and/or clear inputs return to their inact iv e (H I GH) level.

Order Number Package Number Package Description

DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

PR CLR CLK J K Q Q

LHXXX H L
HLXXX L H
LLXXXH

(Note 1)H(Note 1)

HH



LLQ0Q

0

HH



HL H L

HH



LH L H

HH



H H Toggle

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DM7476

Absolute Maximum Ratings(Note 2)

Note 2: The “Absolute Maximum Ratin gs” are those v alues beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s
for actual device operation.

Recommended Operating Conditions

Note 3: TA = 25°C and VCC = 5V.
Note 4: The symbol (↑, ↓) indicates the edge of the cl oc k pulse is used for referen c e (↑) for rising edge, (↓) for falling edge.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Clear is measured with preset HIGH and preset is measured with clear HIGH.

Note 7: Not more than one output should be shorted at a time.
Note 8: With all outputs OPEN, I

CC

is measured with the Q and Q outputs HIGH in turn. At the t im e of m easurement the clock input is grounded.

Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −0.4 mA

I

OL

LOW Level Output Current 16 mA

f

CLK

Clock Frequency (Note 3) 0 15 MHz

t

W

Pulse Width Clock HIGH 20
(Note 3) Clock LOW 47

ns

Preset LOW 25
Clear LOW 25

t

SU

Input Setup Time (Note 3)(Note 4) 0↑ ns

t

H

Input Hold Time (Note 3)(Note 4) 0↓ ns

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 5)

V

I

Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.4 3.4 V

Output Voltage VIL = Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max

0.2 0.4 V

Output Voltage VIH = Min, VIL = Max

I

I

Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

I

IH

HIGH Level VCC = Max J, K 40
Input Current VI = 2.4V Clock 80

µA

Clear 80
Preset 80

I

IL

LOW Level VCC = Max J, K −1.6
Input Current VI = 0.4V Clock −3.2

mA

(Note 6) Clear −3.2

Preset −3.2

I

OS

Short Circuit Output Current VCC = Max (Note 7) −18 −55 mA

I

CC

Supply Current VCC = Max (Note 8) 18 34 mA